Chapter 10 Memory Subsystem.pdf

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Public Version SDRAM Controller (SDRC) Subsystem www.ti.com Address Offset 0x0000 0158 Table 10-133. SMS_CLASS_ARBITER2 Physical Address 0x6C00 0158 Instance SMS Description This register controls the arbitration parameters between the class 2 request groups. Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED BURST-COMPLETE RESERVED EXTENDEDGRANT RESERVED Bits Field Name Description Type Reset 31:30 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x0 29:26 BURST-COMPLETE Delayed service until burst request complete RW 0x0 BurstComplete[k], k= 2 to 5 (BURST-COMPLETE[29] is for group number 5, BURST-COMPLETE[28] is for group number 4, BURST-COMPLETE[27] is for group number 3, BURST-COMPLETE[26] is for group number 2) 0x0: Group #k request to arbiter issued as soon as the first burst request is available 0x1: Group #k request to arbiter delayed until a complete burst transaction is buffered 25:20 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x00 19:12 EXTENDEDGRANT Vector specifying the number of consecutive services a group is RW 0x55 granted. 2 bits per group ExtendedGrant[2*k+1,2*k], k = 2 to 5 (EXTENDEDGRANT[19:18] is for group number 5, EXTENDEDGRANT[17:16] is for group number 4, EXTENDEDGRANT[15:14] is for group number 3, EXTENDEDGRANT[13:12] is for group number 2) 0x1: 1 service for group #k when granted 0x2: 2 services for group #k when granted 0x3: 3 services for group #k when granted 11:6 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x00 5:2 HIGHPRIOVECTOR Vector allocating a higher priority to one of the class members. A RW 0x0 single group may be given this attribute at a time. HighPrioVector[k], k= 2 to 5 (HIGHPRIOVECTOR[5] is for group number 5, HIGHPRIOVECTOR[4] is for group number 4, HIGHPRIOVECTOR[3] is for group number 3, HIGHPRIOVECTOR[2] is for group number 2) 0x0: Group #k has standard priority (LRU based). 0x1: Group #k has the highest priority over all other class members. 1:0 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x0 Table 10-134. Register Call Summary for Register SMS_CLASS_ARBITER2 SDRAM Controller (SDRC) Subsystem • Arbitration Policy: [0] [1] • Memory-Access Scheduler Configuration: [2] • Arbitration Decision: [3] • SMS Register Summary: [4] 2290Memory Subsystem SPRUGN4L–May 2010–Revised June 2011 Copyright © 2010–2011, Texas Instruments Incorporated HIGHPRIOVECTOR RESERVED
Public Version www.ti.com SDRAM Controller (SDRC) Subsystem Address Offset 0x0000 0160 Table 10-135. SMS_INTERCLASS_ARBITER Physical Address 0x6C00 0160 Instance SMS Description This register controls the PWM counter that defines the priority alternation between class 1 and class 2. Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED CLASS2PRIO RESERVED CLASS1PRIO Bits Field Name Description Type Reset 31:24 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x00 23:16 CLASS2PRIO Class 2 high-priority window width (clock cycle count). Do not set to RW 0x40 0x00. 15:8 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x00 7:0 CLASS1PRIO Class 1 high-priority window width (clock cycle count). Do not set to RW 0x40 0x00. Table 10-136. Register Call Summary for Register SMS_INTERCLASS_ARBITER SDRAM Controller (SDRC) Subsystem • Arbitration Decision: [0] [1] • SMS Register Summary: [2] Table 10-137. SMS_CLASS_ROTATIONm Address Offset 0x0000 0164 + (0x0000 0004 * m) Index m = 0 to 2 Physical Address 0x6C00 0164 + (0x0000 0004 * m) Instance SMS Description This register controls the number of consecutive services that is allocated to a thread whose transactions have been split by the rotation engine. Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED NOFSERVICES Bits Field Name Description Type Reset 31:5 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x0000000 4:0 NOFSERVICES Number of RE split transactions serviced consecutively when the RW 0x01 thread gets granted by the arbitration logic. Table 10-138. Register Call Summary for Register SMS_CLASS_ROTATIONm SDRAM Controller (SDRC) Subsystem • Arbitration Policy: [0] • Arbitration Granularity: [1] • SMS Register Summary: [2] SPRUGN4L–May 2010–Revised June 2011 Memory Subsystem Copyright © 2010–2011, Texas Instruments Incorporated 2291
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This chapter describes the memory s
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Device GPMC External device/ memory
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Public Version www.ti.com General-P
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1 GBytes 512 MBytes 256 MBytes 128
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] (co
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
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nCS nBE0/CLE nWE nADV/ALE CSONTIME=
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nCS nBE0/CLE nWE Public Version www
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Row 0 Row 1 Row 2 Row 3 Row 252 Row
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512 Bytes input Row 0 Row 1 Row 2 R
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M0 Manual mode Rd/Wr/ SW Mode Size0
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M1 M2 M3 M4 Per-sector spares Spare
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M9 Per-sector spares, separate ECC
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GPMC_FCLK nCS nBE0/CLE nOE/nRE nADV
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Device GPMC module A [27:17] A [16:
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FCLK CLK nADV nCS nOE A/D bus ClkAc
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FCLK nCS nADV nWE A/D bus AdvWrOffT
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Public Version www.ti.com SDRAM Con
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Device SDRAM controller subsystem R
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MUX1 System address 31 30 29 28 27
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MUX23 System address Address mappin
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Configuration register file Rotatio
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Level 0 Region 0 Public Version www
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OCP slave interface OCP slave port
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BANKALLOCATION = 0b00 BANKALLOCATIO
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Endianism CSnMUXCFG field SDRC.SDRC
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