Chapter 10 Memory Subsystem.pdf

More documents

Recommendations

Info

Public Version General-Purpose Memory Controller www.ti.com CAUTION Although the GPMC interface can drive up to 8 chip-selects, the frequency specified for this interface is for a specific load. If this load is exceeded, the maximum frequency cannot be reached. 10.1.5.2 Access Protocol Configuration 10.1.5.2.1 Supported Devices The access protocol of each chip-select can be independently specified through the GPMC.GPMC_CONFIG1_i[11:10] DEVICETYPE parameter (where i =0 to 7) for: • Random-access synchronous or asynchronous memory like NOR flash, SRAM • NAND flash asynchronous devices NOTE: NAND flash interfacing requires the parameter settings of generic chip-select 0. For more information about the NAND flash GPMC basic programming model and NAND support, see Section 10.1.5.14, NAND Device Basic Programming Model, and Section 10.1.5.14.1, NAND Memory Device in Byte or Word 16 Stream Mode. 10.1.5.2.2 Access Size Adaptation and Device Width Each chip-select can be independently configured through the GPMC.GPMC_CONFIG1_i[13:12] DEVICESIZE field (i = 0 to 7) to interface with a 16-bit wide device or an 8-bit-wide device. System requests with data width greater than the external device data bus width are split into successive accesses according to both the external device data-bus width and little-endian data organization. NOTE: The device does not provide the A0 byte address line required for random-byte addressable 8-bit-wide device interfacing (for both multiplexed and nonmultiplexed protocol). It limits the use of 8-bit-wide device interfacing to byte-alias accesses. This limitation is not applicable to NAND device interfacing (8-bit wide or 16-bit wide devices). 10.1.5.2.3 Address/Data-Multiplexing Interface For random synchronous or asynchronous memory interfacing (DEVICETYPE = 0b00), an address- and data-multiplexing protocol can be selected through the GPMC.GPMC_CONFIG1_i[9] MUXADDDATA bit (i = 0 to 7). The nADV signal must be used as the external device address latch control signal. For the associated chip-select configuration, nADV assertion and deassertion time and nOE assertion time must be set to the appropriate value to meet the address latch setup/hold time requirements of the external device. See Section 10.1.3, GPMC Integration. NOTE: This address/data-multiplexing interface is not applicable to NAND device interfacing. NAND devices require a specific address, command, and data multiplexing protocol. See Section 10.1.5.14, NAND Device Basic Programming Model. 10.1.5.2.4 Address and Data Bus See Section 10.1.3.3, GPMC Address and Data Bus. 10.1.5.2.5 Asynchronous and Synchronous Access For each chip-select configuration, the read access can be specified as either asynchronous or synchronous access through the GPMC.GPMC_CONFIG1_i[29] READTYPE bit (i = 0 to 7). For each chip-select configuration, the write access can be specified as either synchronous or asynchronous access through the GPMC.GPMC_CONFIG1_i[27] WRITETYPE bit (i = 0 to 7). 2108 Memory Subsystem SPRUGN4L–May 2010–Revised June 2011 Copyright © 2010–2011, Texas Instruments Incorporated
Public Version www.ti.com General-Purpose Memory Controller Asynchronous and synchronous read (write) access time and related control signals are controlled through timing parameters that refer to GPMC_FCLK. The primary difference of synchronous mode is the availability of a configurable clock interface (GPMC_CLK) to control the external device. Synchronous mode also affects data-capture and wait-pin monitoring schemes in read access. For details about asynchronous and synchronous access, see the descriptions of GPMC_CLK, RdAccessTime, WrAccessTime, and wait-pin monitoring. For more information about timing-parameter settings, see the sample timing diagrams in this chapter. NOTE: The address bus and nBE[1:0] are fixed for the duration of a synchronous burst read access, but they are updated for each beat of an asynchronous page-read access. 10.1.5.2.6 Page and Burst Support Each chip-select can be configured to process system single or burst requests into successive single accesses or asynchronous page/synchronous burst accesses, with appropriate access size adaptation. Depending on the external device page or burst capability, read and write accesses can be independently configured through the GPMC. The GPMC_CONFIG1_i[30] READMULTIPLE and GPMC.GPMC_CONFIG1_i[28] WRITMULTIPLE bits (i = 0 to 7) are associated with the READTYPE and WRITETYPE parameters. NOTE: • Asynchronous write page mode is not supported. • 8-bit-wide device support is limited to nonburstable devices (READMULTIPLE and WRITEMULTIPLE are don't care). • Not applicable to NAND device interfacing. 10.1.5.2.7 System Burst Versus External Device Burst Support The device system can issue the following requests to the GPMC: • Byte, Word16, Word32 requests (byte enable controlled). This is always a single request from the interconnect point of view. • Incrementing fixed-length bursts of two words, four words, and eight words • Wrapped (critical word access first) fixed-length burst of two, four, or eight words To process a system request with the optimal protocol, the READMULTIPLE (and READTYPE) and WRITEMULTIPLE (and WRITETYPE) parameters must be set according to the burstable capability (synchronous or asynchronous) of the attached device. The GPMC access engine issues only fixed-length burst. The maximum length that can be issued is defined per CS by the GPMC.GPMC_CONFIG1_i[24:23] ATTACHEDDEVICEPAGELENGTH field (i = 0 to 7). When the ATTACHEDDEVICEPAGELENGTH value is less than the system burst request length (including the appropriate access size adaptation according to the device width), the GPMC splits the system burst request into multiple burst beats. Within the specified 4-, 8-, or 16-word value, the ATTACHEDDEVICEPAGELENGTH field value must correspond to the maximum-length burst supported by the memory device configured in fixed-length burst mode (as opposed to continuous burst mode). To get optimal performance from memory devices that natively support 16 Word16-length-wrapping burst capability (critical word access first), the ATTACHEDDEVICEPAGELENGTH parameter must be set to 16 words and the GPMC.GPMC_CONFIG1_i[31] WRAPBURST bit (i = 0 to 7) must be set to 1. Similarly DEVICEPAGELENGTH is set to 4 and 8 for memories supporting respectively 4 and 8 Word16-length-wrapping burst. When the memory device does not offer (or is not configured to offer) native 16 Word16-length-wrapping burst, the WRAPBURST parameter must be cleared, and the GPMC access engine emulates the wrapping burst by issuing the appropriate burst sequences according to the ATTACHEDDEVICEPAGELENGTH value. SPRUGN4L–May 2010–Revised June 2011 Memory Subsystem Copyright © 2010–2011, Texas Instruments Incorporated 2109
Page 1 and 2: This chapter describes the memory s
Page 3 and 4: Device GPMC External device/ memory
Page 5 and 6: Public Version www.ti.com General-P
Page 13: 1 GBytes 512 MBytes 256 MBytes 128
Page 17 and 18: GPMC_FCLK GPMC_CLK gpmc_a[11:1] (co
Page 25 and 26: GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
Page 43 and 44: GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
Page 47 and 48: nCS nBE0/CLE nWE nADV/ALE CSONTIME=
Page 49 and 50: nCS nBE0/CLE nWE Public Version www
Page 53 and 54: Row 0 Row 1 Row 2 Row 3 Row 252 Row
Page 55 and 56: 512 Bytes input Row 0 Row 1 Row 2 R
Page 61 and 62: M0 Manual mode Rd/Wr/ SW Mode Size0
Page 65 and 66:
M1 M2 M3 M4 Per-sector spares Spare
Page 67 and 68:
M9 Per-sector spares, separate ECC
Page 69 and 70:
Public Version www.ti.com General-P
Page 71 and 72:
Page 73 and 74:
GPMC_FCLK nCS nBE0/CLE nOE/nRE nADV
Page 75 and 76:
Device GPMC module A [27:17] A [16:
Page 77 and 78:
FCLK CLK nADV nCS nOE A/D bus ClkAc
Page 79 and 80:
FCLK nCS nADV nWE A/D bus AdvWrOffT
Page 81 and 82:
Page 83 and 84:
Page 85 and 86:
Page 87 and 88:
Page 89 and 90:
Page 91 and 92:
Page 93 and 94:
Page 95 and 96:
Page 97 and 98:
Page 99 and 100:
Page 101 and 102:
Page 103 and 104:
Page 105 and 106:
Page 107 and 108:
Page 109 and 110:
Page 111 and 112:
Public Version www.ti.com SDRAM Con
Page 113 and 114:
Page 115 and 116:
Device SDRAM controller subsystem R
Page 117 and 118:
Page 119 and 120:
MUX1 System address 31 30 29 28 27
Page 121 and 122:
MUX23 System address Address mappin
Page 123 and 124:
Page 125 and 126:
Configuration register file Rotatio
Page 127 and 128:
Page 129 and 130:
Page 131 and 132:
Level 0 Region 0 Public Version www
Page 133 and 134:
Page 135 and 136:
OCP slave interface OCP slave port
Page 137 and 138:
Page 139 and 140:
BANKALLOCATION = 0b00 BANKALLOCATIO
Page 141 and 142:
Page 143 and 144:
Endianism CSnMUXCFG field SDRC.SDRC
Page 145 and 146:
Page 147 and 148:
Page 149 and 150:
CLK CMD WRITE DQ DQS CLK CMD DQ DQS
Page 151 and 152:
CLK_IN SIGNAL_IN MODEMAXDELAY Initi
Page 153 and 154:
Page 155 and 156:
Page 157 and 158:
Page 159 and 160:
Page 161 and 162:
Page 163 and 164:
Page 165 and 166:
Page 167 and 168:
8 bits 32 bits Y0 U Y1 V P0 P1 16 b
Page 169 and 170:
Start configuration of VRFB context
Page 171 and 172:
Initiator: Camera subsystem SDRC Su
Page 173 and 174:
Page 175 and 176:
Request for transaction on class 1
Page 177 and 178:
Class 1 and class 2 request for tra
Page 179 and 180:
No A Class 0 empty? Yes Class 1 emp
Page 181 and 182:
Status: There are n pending request
Page 183 and 184:
4 GB 0x0000 0000 0x6C00 0000 0x6CFF
Page 185 and 186:
Page 187 and 188:
Page 189 and 190:
Page 191 and 192:
Page 193 and 194:
Page 195 and 196:
Page 197 and 198:
Page 199 and 200:
Page 201 and 202:
Page 203 and 204:
Page 205 and 206:
Page 207 and 208:
Page 209 and 210:
Page 211 and 212:
Page 213 and 214:
Page 215 and 216:
Page 217 and 218:
Page 219 and 220:
Device D2D OCM_ROM OCM_RAM ROM (32K
Page 221 and 222:
Public Version www.ti.com On-Chip M
show all

Chapter 10 Memory Subsystem.pdf

Create successful ePaper yourself

Delete template?

Save as template?