Chapter 10 Memory Subsystem.pdf

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Public Version General-Purpose Memory Controller www.ti.com • One DMA request goes from GPMC (GPMC_DMA_REQ) to the system DMA (sDMA) : S_DMA_3. 10.1.3.3 GPMC Address and Data Bus The current application supports GPMC connection to address/data-multiplexed memory and a NAND device. Connection to a nonmultiplexed address/data memory is supported with an address range of only 2 Kbytes. Depending on the GPMC configuration on each chip-select, address and data-bus lines that are not required for a particular access protocol are not updated (changed from current value) and are not sampled when input (input data bus). The current application supports GPMC connection to address/data-multiplexed memory, address/data-nonmultiplexed memory with limited address (2 Kbytes), and a NAND device: • When the GPMC.GPMC_CONFIG[1] LIMITEDADDRESS bit is set to 1, only gpmc_a[11:1] address lines are used. This limits the memory support to 2K-byte addressable memories. • For address/data-multiplexed NOR devices, the address is multiplexed on the data bus. • 8-bit wide NOR devices do not use GPMC I/O: gpmc_d[15:8] for data (they are used for address if needed). • 16-bit wide NAND devices do not use GPMC I/O: gpmc_a[11:1] . • 8-bit wide NAND devices do not use GPMC I/O: gpmc_a[11:1] and GPMC I/O: gpmc_d[15:8]. CAUTION Before trying to access a chip-select configured with a nonmultiplexed protocol, set the LIMITEDADDRESS bit control. 10.1.3.3.1 GPMC I/O Configuration Setting (in Default Pinout Mode 0) NOTE: In this section, the i in GPMC_CONFIG1_i stands for the GPMC chip-select i where i = 0 to 7. The address/data-nonmultiplexed device, which is limited to a 2K-byte address range, is selected by programming the following register fields: • GPMC.GPMC_CONFIG1_i[11:10] DEVICETYPE field = 0x00 • GPMC.GPMC_CONFIG1_i[9] MUXADDDATA bit = 0 • GPMC.GPMC_CONFIG[1] LIMITEDADDRESS bit = 1 NOTE: The LIMITEDADDRESS field applies only to address/data-nonmultiplexed devices; it has no effect on other device types (address/data-multiplexed, NAND). To select the address/data-multiplexed device, program the following register fields: • GPMC.GPMC_CONFIG1_i[11:10] DEVICETYPE field = 0b00 • GPMC.GPMC_CONFIG1_i[9] MUXADDDATA bit = 1 To select the NAND device, program the following register field: • GPMC.GPMC_CONFIG1_i[11:10] DEVICETYPE field = 0b10 • GPMC.GPMC_CONFIG1_i[9] MUXADDDATA bit = 0 10.1.3.3.2 GPMC CS0 Default Configuration at IC Reset To ensure a correct external boot with a GPMC access from IC reset time on CS0, several external pins are sampled: • The sys_boot[4:0] pins (device boundary) define the sequence of interfaces and devices to use for booting. 2102 Memory Subsystem SPRUGN4L–May 2010–Revised June 2011 Copyright © 2010–2011, Texas Instruments Incorporated
Public Version www.ti.com General-Purpose Memory Controller • The sys_boot[5] pin defines which group of booting sequences is preferred: memory booting (sys_boot[5] = 0) or peripheral booting (sys_boot[5] = 1). • Three additional pins are used to configure reset values in the GPMC.GPMC_CONFIG1_i register (where i = 0): – The bootwaiten input pin (GPMC boundary) enables the monitoring on chip-select 0 of the WAIT pin at IC reset release time for read accesses. The input pin is used to configure the GPMC.GPMC_CONFIG1_i[22] WAITREADMONITORING bit (where i = 0). Its value comes from the BOOT_WAIT_ENABLE signal generated by the system control module (SCM). When sys_boot[5:0] = 0b111111, the BOOT_WAIT_ENABLE signal is activated, causing the wait pin to be monitored for read access. – The bootdevicesize input pin (GPMC boundary) defines the size of the attached device on chip-select 0 and is used to configure the GPMC.GPMC_CONFIG1_i[13:12] DEVICESIZE bits (where i = 0). A BOOT_DEVICE_SIZE signal is propagated from the SCM. Its value is fixed at 0x1 at IC reset, causing a 16-bit wide external memory to be used. – The cs0muxdevice input pin (GPMC boundary) selects whether the attached device to chip-select 0 is a multiplexed address and data device or not. The input pin is used to configure the GPMC.GPMC_CONFIG1_i[9] MUXADDDATA bit (where i = 0). A CS0_MUX_DEVICE signal is propagated from the SCM. Its value is fixed at 0x1 at IC reset, causing the attached device to be address/data-multiplexed. – The waitselectpin input pin selects the WAIT signal at IC reset release time between WAIT0 input pin or WAIT1 input pin. At IC reset release time, these two pins have different polarity. CAUTION Using the internal boot code, the entire CS0 configuration can be modified before the first CS0 access. This modification of internal boot code is necessary for two external devices: • NAND device attached to CS0 • Nonmultiplexed 2-Kbyte address range device attached to CS0 At reset time, the IC may boot from the internal ROM or from the memory attached to the GPMC chip-select 0. This selection is made outside the GPMC. Reset values of the timing control parameters are defined to cope with direct boot on address and data multiplexed NOR Flash device, on non-multiplexed NOR Flash device or on any asynchronous device with large timing margins assuming a low GPMC_FCLK frequency (for example, 19.2Mhz) at boot time. 10.1.4 GPMC Functional Description 10.1.4.1 Description As Figure 10-5 shows, the GPMC consists of six blocks: • L3 interconnect port interface • Address decoder, GPMC configuration, and chip-select configuration register file • Access engine • Prefetch and write-posting engine • Error correction code engine (ECC) • External device/memory port interface SPRUGN4L–May 2010–Revised June 2011 Memory Subsystem Copyright © 2010–2011, Texas Instruments Incorporated 2103
Page 1 and 2: This chapter describes the memory s
Page 3 and 4: Device GPMC External device/ memory
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Page 13 and 14: 1 GBytes 512 MBytes 256 MBytes 128
Page 17 and 18: GPMC_FCLK GPMC_CLK gpmc_a[11:1] (co
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M0 Manual mode Rd/Wr/ SW Mode Size0
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M1 M2 M3 M4 Per-sector spares Spare
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M9 Per-sector spares, separate ECC
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GPMC_FCLK nCS nBE0/CLE nOE/nRE nADV
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Device GPMC module A [27:17] A [16:
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FCLK CLK nADV nCS nOE A/D bus ClkAc
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Public Version www.ti.com SDRAM Con
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Device SDRAM controller subsystem R
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MUX1 System address 31 30 29 28 27
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MUX23 System address Address mappin
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Configuration register file Rotatio
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OCP slave interface OCP slave port
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BANKALLOCATION = 0b00 BANKALLOCATIO
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Endianism CSnMUXCFG field SDRC.SDRC
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CLK CMD WRITE DQ DQS CLK CMD DQ DQS
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8 bits 32 bits Y0 U Y1 V P0 P1 16 b
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Initiator: Camera subsystem SDRC Su
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Request for transaction on class 1
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Class 1 and class 2 request for tra
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No A Class 0 empty? Yes Class 1 emp
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4 GB 0x0000 0000 0x6C00 0000 0x6CFF
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Device D2D OCM_ROM OCM_RAM ROM (32K
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