Chapter 10 Memory Subsystem.pdf

More documents

Recommendations

Info

Bank0 Bank1 Bank2 Bank3 Row0 Row0 Bank0 Row0 Bank0 Row1 Row0 Bank1 Row0 Bank1 Row2 Row1 Bank0 Row0 Bank2 ... Row1 Bank1 Row0 Bank3 Row2 Bank0 Row1 Bank0 Row2 Bank1 Row1 Bank1 ... Row1 Bank2 Row1 Bank3 Row n Bank0, Row2 Bank0 Row0 Row1 Row2 ... Bank1 Row2 Bank1 ... Row n Row0 Row1 Row2 ... Row n Row0 Row1 Row2 ... Row n Public Version SDRAM Controller (SDRC) Subsystem www.ti.com Figure 10-54. Simplified View of Bank-Row-Column vs Row-Bank-Column Bank Allocation Bank2, Bank3 Row n Bank0 Row n Bank1 Row0 Bank2 Row0 Bank3 Row1 Bank2 Row1 Bank3 Row2 Bank2 Row2 Bank3 ... Bank-Row-Column Bank1-Row- Bank0-Column Row n Bank2 Row n Bank2 Row n Bank3 Row n Bank3 Row-Bank-Column (Interleaved mode) sdrc_044 The latency to charge another row in the same bank (that is, to close the opened page and to open another one) is bigger than the latency involved with an access to a given row in another bank. By moving bank select signals ahead of column and after row addresses, bank interleaving is likely to happen more often. More frequent use of the interleaved mode means less overall SDRAM access time and, thus, yields to better overall performance. In some use cases, several initiators access the same bank (bank0 for instance) in external SDRAM memory at the same time. With this kind of scenario, a lot of penalties are added because of rows opening and closing. The BANKALLOCATION setting improves the latency for reading and writing operations by optimizing memory accesses through the reduction of deactivate sequence use, thereby reducing time penalties. The bank1-row-bank0-column allocation is a good compromise between the legacy bank allocation (bank-row-column) and the full interleaving bank allocation (row-bank-column). In some use cases, it may be necessary to keep only half of the memory refreshed (on bank0 and bank1 for instance) while the other two banks are unused. In full interleaving bank allocation, the memory must be refreshed through the self-refresh mode, while with bank1-row-bank0-column, the memory can be refreshed through self-refresh mode or through partial array self-refresh mode. In the following, an example of latency is given based on a 512-Mbit SDRAM memory data sheet. Table 10-101 gives the duration for some AC timing parameters. The frequency used in the example is 133 MHz ( that is, tCK = 7.5 ns). The CAS latency = 3. Table 10-101. Mobile DDR SDRAM AC Timing Parameters AC Timing Parameter Description Duration (ns) tRFC Autorefresh cycle time 80 (min) tRP Row precharge time 22.5 (or 3 tCK) 2234 Memory Subsystem SPRUGN4L–May 2010–Revised June 2011 Copyright © 2010–2011, Texas Instruments Incorporated
Public Version www.ti.com SDRAM Controller (SDRC) Subsystem Table 10-101. Mobile DDR SDRAM AC Timing Parameters (continued) AC Timing Parameter Description Duration (ns) tRC Row cycle time 67.5 (or 9 tCK) tRAS Row active time 45 (or 6 tCK) tRCD nRAS to nCAS delay time 22.5 (or 3 tCK) tRRD Row active to row active delay time 15 (or 2 tCK) The latency to access another row in the same bank depends on tRP and tRAS timings because a precharge command followed by an active command must be issued. Therefore, 6 tCK are needed to close the current row and open another one. When accessing another bank, the latency to access another row depends on tRAS timing only because the closing of the current row is not mandatory. In other words only an active command must be issued. Therefore, 3 tCK are needed to open another row in a different bank. Single initiator use case: When the initiator wants to access a page in a bank for the first time, it opens only this page. It takes 3 tCK. When the initiator is done with this page, it closes this page and opens another one. It takes 6 tCK. Two initiators use case: When one initiator wants to access a page in the same bank, it must necessarily close the current page and open the page it wants to access. It takes 6 tCK. When one initiator wants to access a page this time in another bank, there can be less page opening and closing. For instance, if the initiator wants to open a page in another bank where no page is open, it takes only 3 tCK, rather than 6 tCK if it was another page in the same bank. 10.2.4.4.5 Data Multiplexing During Write Operations 10.2.4.4.5.1 External Bus Combinations The SDRC pin allocation scenarios are provided in Table 10-102. These scenarios are defined on a per-CS basis for maximum flexibility. The pin allocation configurations allow implementation of combinations of the 16-/32-bit external interfaces listed in this table. The data multiplexer receives a 64-bit word from the SDRAM command queue and partitions the data into a series of 16-bit or 32-bit accesses. The data multiplexer also steers the data to the appropriate data lane. The data partitioning and data steering are determined by the SDRC.SDRC_SHARING[11:9] CS0MUXCFG and SDRC.SDRC_SHARING[14:12] CS1MUXCFG fields. Table 10-102. SDRC Data Lane Configurations Device sdrc_d[31:24] sdrc_d[23:16] sdrc_d[15:8] sdrc_d[7:0] pins DataLane[31:16] DataLane[15:0] DQS3 DQS2 DQS1 DQS0 DQM3 DQM2 DQM1 DQM0 SDRC.SDRC_SHARING[14:9] CSnMUXCFG field D[31:0] 0x0, 0x1 D[15:0] 0x2, 0x7 D[15:0] 0x3 0x4, 0x5, 0x6: Reserved SPRUGN4L–May 2010–Revised June 2011 Memory Subsystem Copyright © 2010–2011, Texas Instruments Incorporated 2235
Page 1 and 2:
This chapter describes the memory s
Page 3 and 4:
Device GPMC External device/ memory
Page 5 and 6:
Public Version www.ti.com General-P
Page 7 and 8:
Page 9 and 10:
Page 11 and 12:
Page 13 and 14:
1 GBytes 512 MBytes 256 MBytes 128
Page 15 and 16:
Page 17 and 18:
GPMC_FCLK GPMC_CLK gpmc_a[11:1] (co
Page 19 and 20:
Page 21 and 22:
Page 23 and 24:
Page 25 and 26:
GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
Page 27 and 28:
Page 29 and 30:
Page 31 and 32:
Page 33 and 34:
Page 35 and 36:
Page 37 and 38:
Page 39 and 40:
Page 41 and 42:
Page 43 and 44:
GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
Page 45 and 46:
Page 47 and 48:
nCS nBE0/CLE nWE nADV/ALE CSONTIME=
Page 49 and 50:
nCS nBE0/CLE nWE Public Version www
Page 51 and 52:
Page 53 and 54:
Row 0 Row 1 Row 2 Row 3 Row 252 Row
Page 55 and 56:
512 Bytes input Row 0 Row 1 Row 2 R
Page 57 and 58:
Page 59 and 60:
Page 61 and 62:
M0 Manual mode Rd/Wr/ SW Mode Size0
Page 63 and 64:
Page 65 and 66:
M1 M2 M3 M4 Per-sector spares Spare
Page 67 and 68:
M9 Per-sector spares, separate ECC
Page 69 and 70:
Page 71 and 72:
Page 73 and 74:
GPMC_FCLK nCS nBE0/CLE nOE/nRE nADV
Page 75 and 76:
Device GPMC module A [27:17] A [16:
Page 77 and 78:
FCLK CLK nADV nCS nOE A/D bus ClkAc
Page 79 and 80:
FCLK nCS nADV nWE A/D bus AdvWrOffT
Page 81 and 82:
Page 83 and 84:
Page 85 and 86:
Page 87 and 88:
Page 89 and 90: Public Version www.ti.com General-P
Page 111 and 112: Public Version www.ti.com SDRAM Con
Page 115 and 116: Device SDRAM controller subsystem R
Page 119 and 120: MUX1 System address 31 30 29 28 27
Page 121 and 122: MUX23 System address Address mappin
Page 125 and 126: Configuration register file Rotatio
Page 131 and 132: Level 0 Region 0 Public Version www
Page 135 and 136: OCP slave interface OCP slave port
Page 139: BANKALLOCATION = 0b00 BANKALLOCATIO
Page 143 and 144: Endianism CSnMUXCFG field SDRC.SDRC
Page 149 and 150: CLK CMD WRITE DQ DQS CLK CMD DQ DQS
Page 151 and 152: CLK_IN SIGNAL_IN MODEMAXDELAY Initi
Page 167 and 168: 8 bits 32 bits Y0 U Y1 V P0 P1 16 b
Page 169 and 170: Start configuration of VRFB context
Page 171 and 172: Initiator: Camera subsystem SDRC Su
Page 175 and 176: Request for transaction on class 1
Page 177 and 178: Class 1 and class 2 request for tra
Page 179 and 180: No A Class 0 empty? Yes Class 1 emp
Page 181 and 182: Status: There are n pending request
Page 183 and 184: 4 GB 0x0000 0000 0x6C00 0000 0x6CFF
Page 191 and 192:
Public Version www.ti.com SDRAM Con
Page 193 and 194:
Page 195 and 196:
Page 197 and 198:
Page 199 and 200:
Page 201 and 202:
Page 203 and 204:
Page 205 and 206:
Page 207 and 208:
Page 209 and 210:
Page 211 and 212:
Page 213 and 214:
Page 215 and 216:
Page 217 and 218:
Page 219 and 220:
Device D2D OCM_ROM OCM_RAM ROM (32K
Page 221 and 222:
Public Version www.ti.com On-Chip M
show all

Chapter 10 Memory Subsystem.pdf

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?