Chapter 10 Memory Subsystem.pdf

More documents

Recommendations

Info

Public Version General-Purpose Memory Controller www.ti.com • GPMC.GPMC_CONFIG1_i register settings: – WRITEMULTIPLE bit at 1 (write multiple access) – WRITETYPE bit at 1 (write synchronous) – MUXADDDATA bit at 1 (address/data-multiplexed device) When WRACCESSTIME completes, control-signal timings are frozen during the multiple data transactions, corresponding to the PAGEBURSTACCESSTIME multiplied by the number of remaining data transactions. • Chip-select signal nCS: – nCS assertion time is controlled by the GPMC.GPMC_CONFIG2_i[3:0] CSONTIME field and ensures address setup time to nCS assertion. – nCS deassertion time controlled by the GPMC.GPMC_CONFIG2_i[20:16] CSWROFFTIME field and ensures address hold time to nCS deassertion. • Address valid signal nADV: – nADV assertion time is controlled by the GPMC.GPMC_CONFIG3_i[3:0] ADVONTIME field. – nADV deassertion time is controlled by the GPMC.GPMC_CONFIG3_i[20:16] ADVWROFFTIME field. • Write enable signal nWE: – nWE assertion indicates a write cycle. – nWE assertion time is controlled by the GPMC.GPMC_CONFIG4_i[19:16] WEONTIME field. – nWE deassertion time is controlled by the GPMC.GPMC_CONFIG4_i[28:24] WEOFFTIME field. NOTE: The nWE falling edge must not be used to control the time when the burst first data is driven in the address / data bus because some new devices require the nWE signal at low during the address phase. • First write data is driven by the GPMC at WRDATAONADMUXBUS (GPMC_CONFIG6_i[19:16]), when in address/data mux configuration. The next write data of the burst is driven on the bus at WRACCESSTIME + 1 during PAGEBURSTACCESSTIME GPMC_FCLK cycles. The last data of the synchronous burst write is driven until WRCYCLETIME completes. – WRACCESSTIME is defined in the GPMC.GPMC_CONFIG5_i register. – The PAGEBURSTACCESSTIME parameter must be set accordingly with GPMCFCLKDIVIDER and the memory-device internal configuration. • Total access time (WRCYCLETIME) corresponds to WRACCESSTIME plus the address hold time from nCS deassertion, plus time from WRACCESSTIME to CSWROFFTIME. – WRCYCLETIME is defined in the GPMC.GPMC_CONFIG5_i register. – In Figure 10-20, the WRCYCLETIME programmed value equals WRCYCLETIME0 + WRCYCLETIME1. • Direction signal DIR: DIR is OUT during the entire access. After a write operation, if no other access (read or write) is pending, the data bus keeps the previous value. See Section 10.1.5.3.10, Bus Keeping Support. Figure 10-21 shows the same synchronous burst write access when the chip-select is configured in address/data-multiplexed mode. 2136 Memory Subsystem SPRUGN4L–May 2010–Revised June 2011 Copyright © 2010–2011, Texas Instruments Incorporated
GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpmc_d[15:0] nBE1nBE0 nCS nADV nWE DIR WAIT Valid Address WRDATAONADMUXBUS Valid Address D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 7 CSWROFFTIME CSONTIME ADVWROFFTIME ADVONTIME WEONTIME WRCYCLETIME0 WRACCESSTIME PAGEBURSTACCESSTIME CLKACTIVATIONTIME WEOFFTIME Public Version www.ti.com General-Purpose Memory Controller Figure 10-21. Synchronous Multiple Write (Burst Write) in Address/Data-Multiplexed Mode PAGEBURSTACCESSTIME OUT PAGEBURSTACCESSTIME WRCYCLETIME1 The first data of the burst is driven on the a/d bus at GPMC_CONFIG6_i[19:16] WRDATAONADMUXBUS. 10.1.5.11 pSRAM Basic Programming Model pSRAM devices are SRAM-pin-compatible low-power memories that contain a self-refreshed DRAM memory array. These devices can be accessed by the GPMC with the GPMC.GPMC_CONFIG1_i[11:10] DEVICETYPE field (i = 0 to 7). The pSRAM devices support the following operations: • Asynchronous single read • Asynchronous page read • Asynchronous single write • Synchronous single read and write • Synchronous burst read • Synchronous burst write pSRAM devices must be powered up and initialized in a predefined manner according to the specifications of the attached device. pSRAM devices can be programmed to use either mode: fixed or variable latency. pSRAM devices can either automatically schedule autorefresh operations, which force the GPMC to use its WAIT signal capability when read or write operations occur during an internal self-refresh operation, or pSRAM devices automatically include the autorefresh operation in the access time. These devices do not require additional WAIT signal capability or a minimum nCS high pulse width between consecutive accesses to ensure that the correct internal refresh operation is scheduled. In both pSRAM cases, the GPMC configuration for this chip-select must be set according to the specifications of the attached device. SPRUGN4L–May 2010–Revised June 2011 Memory Subsystem Copyright © 2010–2011, Texas Instruments Incorporated gpmc-021 2137
Page 1 and 2: This chapter describes the memory s
Page 3 and 4: Device GPMC External device/ memory
Page 5 and 6: Public Version www.ti.com General-P
Page 13 and 14: 1 GBytes 512 MBytes 256 MBytes 128
Page 17 and 18: GPMC_FCLK GPMC_CLK gpmc_a[11:1] (co
Page 25 and 26: GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
Page 41: GPMC_FCLK GPMC_CLK gpmc_a[11:1] (co
Page 47 and 48: nCS nBE0/CLE nWE nADV/ALE CSONTIME=
Page 49 and 50: nCS nBE0/CLE nWE Public Version www
Page 53 and 54: Row 0 Row 1 Row 2 Row 3 Row 252 Row
Page 55 and 56: 512 Bytes input Row 0 Row 1 Row 2 R
Page 61 and 62: M0 Manual mode Rd/Wr/ SW Mode Size0
Page 65 and 66: M1 M2 M3 M4 Per-sector spares Spare
Page 67 and 68: M9 Per-sector spares, separate ECC
Page 73 and 74: GPMC_FCLK nCS nBE0/CLE nOE/nRE nADV
Page 75 and 76: Device GPMC module A [27:17] A [16:
Page 77 and 78: FCLK CLK nADV nCS nOE A/D bus ClkAc
Page 79 and 80: FCLK nCS nADV nWE A/D bus AdvWrOffT
Page 93 and 94:
Public Version www.ti.com General-P
Page 95 and 96:
Page 97 and 98:
Page 99 and 100:
Page 101 and 102:
Page 103 and 104:
Page 105 and 106:
Page 107 and 108:
Page 109 and 110:
Page 111 and 112:
Public Version www.ti.com SDRAM Con
Page 113 and 114:
Page 115 and 116:
Device SDRAM controller subsystem R
Page 117 and 118:
Page 119 and 120:
MUX1 System address 31 30 29 28 27
Page 121 and 122:
MUX23 System address Address mappin
Page 123 and 124:
Page 125 and 126:
Configuration register file Rotatio
Page 127 and 128:
Page 129 and 130:
Page 131 and 132:
Level 0 Region 0 Public Version www
Page 133 and 134:
Page 135 and 136:
OCP slave interface OCP slave port
Page 137 and 138:
Page 139 and 140:
BANKALLOCATION = 0b00 BANKALLOCATIO
Page 141 and 142:
Page 143 and 144:
Endianism CSnMUXCFG field SDRC.SDRC
Page 145 and 146:
Page 147 and 148:
Page 149 and 150:
CLK CMD WRITE DQ DQS CLK CMD DQ DQS
Page 151 and 152:
CLK_IN SIGNAL_IN MODEMAXDELAY Initi
Page 153 and 154:
Page 155 and 156:
Page 157 and 158:
Page 159 and 160:
Page 161 and 162:
Page 163 and 164:
Page 165 and 166:
Page 167 and 168:
8 bits 32 bits Y0 U Y1 V P0 P1 16 b
Page 169 and 170:
Start configuration of VRFB context
Page 171 and 172:
Initiator: Camera subsystem SDRC Su
Page 173 and 174:
Page 175 and 176:
Request for transaction on class 1
Page 177 and 178:
Class 1 and class 2 request for tra
Page 179 and 180:
No A Class 0 empty? Yes Class 1 emp
Page 181 and 182:
Status: There are n pending request
Page 183 and 184:
4 GB 0x0000 0000 0x6C00 0000 0x6CFF
Page 185 and 186:
Page 187 and 188:
Page 189 and 190:
Page 191 and 192:
Page 193 and 194:
Page 195 and 196:
Page 197 and 198:
Page 199 and 200:
Page 201 and 202:
Page 203 and 204:
Page 205 and 206:
Page 207 and 208:
Page 209 and 210:
Page 211 and 212:
Page 213 and 214:
Page 215 and 216:
Page 217 and 218:
Page 219 and 220:
Device D2D OCM_ROM OCM_RAM ROM (32K
Page 221 and 222:
Public Version www.ti.com On-Chip M
show all

Chapter 10 Memory Subsystem.pdf

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?