Chapter 10 Memory Subsystem.pdf
Chapter 10 Memory Subsystem.pdf
Chapter 10 Memory Subsystem.pdf
Create successful ePaper yourself
Turn your PDF publications into a flip-book with our unique Google optimized e-Paper software.
Public Version<br />
www.ti.com SDRAM Controller (SDRC) <strong>Subsystem</strong><br />
Address Offset 0x0000 0160<br />
Table <strong>10</strong>-135. SMS_INTERCLASS_ARBITER<br />
Physical Address 0x6C00 0160 Instance SMS<br />
Description This register controls the PWM counter that defines the priority alternation between class 1 and class 2.<br />
Type RW<br />
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 <strong>10</strong> 9 8 7 6 5 4 3 2 1 0<br />
RESERVED CLASS2PRIO RESERVED CLASS1PRIO<br />
Bits Field Name Description Type Reset<br />
31:24 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x00<br />
23:16 CLASS2PRIO Class 2 high-priority window width (clock cycle count). Do not set to RW 0x40<br />
0x00.<br />
15:8 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x00<br />
7:0 CLASS1PRIO Class 1 high-priority window width (clock cycle count). Do not set to RW 0x40<br />
0x00.<br />
Table <strong>10</strong>-136. Register Call Summary for Register SMS_INTERCLASS_ARBITER<br />
SDRAM Controller (SDRC) <strong>Subsystem</strong><br />
• Arbitration Decision: [0] [1]<br />
• SMS Register Summary: [2]<br />
Table <strong>10</strong>-137. SMS_CLASS_ROTATIONm<br />
Address Offset 0x0000 0164 + (0x0000 0004 * m) Index m = 0 to 2<br />
Physical Address 0x6C00 0164 + (0x0000 0004 * m) Instance SMS<br />
Description This register controls the number of consecutive services that is allocated to a thread whose transactions have<br />
been split by the rotation engine.<br />
Type RW<br />
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 <strong>10</strong> 9 8 7 6 5 4 3 2 1 0<br />
RESERVED NOFSERVICES<br />
Bits Field Name Description Type Reset<br />
31:5 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x0000000<br />
4:0 NOFSERVICES Number of RE split transactions serviced consecutively when the RW 0x01<br />
thread gets granted by the arbitration logic.<br />
Table <strong>10</strong>-138. Register Call Summary for Register SMS_CLASS_ROTATIONm<br />
SDRAM Controller (SDRC) <strong>Subsystem</strong><br />
• Arbitration Policy: [0]<br />
• Arbitration Granularity: [1]<br />
• SMS Register Summary: [2]<br />
SPRUGN4L–May 20<strong>10</strong>–Revised June 2011 <strong>Memory</strong> <strong>Subsystem</strong><br />
Copyright © 20<strong>10</strong>–2011, Texas Instruments Incorporated<br />
2291