Chapter 10 Memory Subsystem.pdf

FCLK
nCS
nADV
nOE
A/D bus
AdvRdOffTime = 1
OeOnTime = 3
Valid Address
Data capture on GPMC side: RdAccessTime = 9
CsReadOffTime = 10
OeOffTime = 10
Memory-side access time
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cycle time.
• Addresses can now be relatched and a new read cycle begun.
Table 10-21. GPMC Timing Parameters for Asynchronous Read Access
Parameter Name Formula Duration (ns) Number of GPMC Register
on GPMC side Clock Cycles Configurations
(F = 104 MHz)
ClkActivationTime n/a (asynchronous mode)
AccessTime round max (tCE) 80 9 ACCESSTIME = 0x09
PageBurstAccess n/a (single access)
Time
RdCycleTime AccessTime + 1cycle + tOEZ 96, 615 11 RDCYCLETIME = 0x0B
CsOnTime tCAS 0 0 CSONTIME = 0x0
CsReadOffTime AccessTime + 1 cycle 89, 615 10 CSRDOFFTIME = 0x0A
AdvOnTime tAAVDS 3 1 ADVONTIME = 0X1
AdvRdOffTime tAAVDS + tAVDP 9 1 ADVRDOFFTIME =
0x01
OeOnTime OeOnTime >= AdvRdOffTime - 3 for instance OEONTIME = 0x3
(multiplexed mode)
OeOffTime AccessTime + 1cycle 89, 615 10 OEOFFTIME = 0x0A
Figure 10-39. Asynchronous Single Read Access (Timing Parameters in Clock Cycles)
Data Setup time
Data Hold time
10.1.6.1.2.3 GPMC Configuration for Asynchronous Single Write Access
The clock runs at 104 MHz: (f = 104 MHz; T = 9, 615 ns).
DATA
RdCycleTime = 11
Table 10-23 shows how to calculate timings for the GPMC using the memory parameters.
tOEZ
Valid Address
Table 10-22 shows the timing parameters (on the memory side) that determine the parameters on the
GPMC side.
Figure 10-40 shows the synchronous burst write access.
Table 10-22. AC Characteristics for Asynchronous Single Write ( Memory Side)
AC Characteristics on the Memory Side Description Duration (ns)
tWC Write cycle time 60
tAVDP nADV low time 6
tWP Write pulse width 25
2172Memory Subsystem SPRUGN4L–May 2010–Revised June 2011
Copyright © 2010–2011, Texas Instruments Incorporated
gpmc-039