Chapter 10 Memory Subsystem.pdf

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4. Program the CMDCODE field of the relevant manual command register to 0001.
This ensures that all banks are idle by executing a precharge all command.
5. Enable DLL by setting the ENADLL field of the relevant SDRC.SDRC_DLLA_CTRL register to 0x1.
The amount of time the SDRC spends in power-down mode must not exceed the refresh period;
otherwise, data becomes corrupted.
10.2.5.4.3.4 Deep-Power-Down Mode Power Management
When in deep-power-down mode the power distribution to the entire memory array is cut. The
programming model for deep-power-down mode is as follows:
Deep-power-down Mode Entry
• Precharge all banks (CMDCODE: 0x1). This ensures that all banks are idle.
• Enter deep-power-down mode (CMDCODE: 0x3).
Deep-power-down Mode Exit
• Exit deep-power-down mode (CMDCODE: 0x4).
The MR and EMR values are retained upon exiting deep-power-down mode.
NOTE: Because power-pown entry/exit sequences depend on memory devices, see the memory
specification for the complete sequence.
10.2.5.4.3.5 Manual Self-Refresh Mode Power Management
The programming model for entering and exiting self-refresh mode is as follows:
Self-Refresh Entry
• Precharge all banks (CMDCODE: 0x1).
• NOP (CMDCODE: 0x0)
• Enter self-refresh mode (CMDCODE: 0x5).
There is no need for the software to disable the autorefresh in the SDRC.SDRC_RFR_CTRL_p register
before entering self-refresh. The autorefresh counter is reset in hardware so that an autorefresh cycle is
automatically generated immediately after a self-refresh exit, and before any other command.
Self-Refresh Exit
• Exit self-refresh mode (CMDCODE: 0x6).
• If needed, reconfigure SDRC registers as required.
• Enable autorefresh by programming:
– The relevant SDRC.SDRC_RFR_CTRL_p[23:8] ARCV field
– The relevant SDRC.SDRC_RFR_CTRL_p[1:0] ARE field to the desired refresh burst
10.2.5.5 Error Management
All data transfers in the SDRC operate a system of full handshaking. A valid read or write request that is
presented to the SDRC by the L3 interconnect sequencer results in the SDRC acknowledging the transfer
by raising the SCmdAccept flag. Failure to do this within a defined temporal window constitutes an error.
Errors can arise from the following sources:
• Any transaction while the memory is in deep-power-down mode
• An illegal initiator access. The address of the last illegal access is captured in the
SDRC.SDRC_ERR_ADDR register
If an error occurs, the software error handler performs the following actions:
• Interrogates the ERRORVALID field of the SDRC.SDRC_ERR_TYPE register to verify the presence of
an error
2258 Memory Subsystem SPRUGN4L–May 2010–Revised June 2011
Copyright © 2010–2011, Texas Instruments Incorporated