Chapter 10 Memory Subsystem.pdf

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Public Version SDRAM Controller (SDRC) Subsystem www.ti.com Table 10-184. Register Call Summary for Register SDRC_RFR_CTRL_p SDRAM Controller (SDRC) Subsystem • Autorefresh Management: [0] [1] [2] • Memory Power Management: [3] [4] [5] • SDRC Register Summary: [6] Table 10-185. SDRC_MANUAL_p Address Offset 0x0000 00A8 + (0x0000 0030 * p) Index p = 0 to 1 Physical Address 0x6D00 00A8 + (0x0000 0030 * p) Instance SDRC Description This register allows to send specific commands to the external memory devices under software control. Any write to this register generates the appropriate sequence based on the command code. Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CMDPARAM RESERVED CMDCODE Bits Field Name Description Type Reset 31:16 CMDPARAM Manual command parameter, if any. RW 0x0000 15:4 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x000 3:0 CMDCODE Memory command opcode; other values reserved for future RW 0x0 implementations. 0x0: NOP command - no parameter 0x1: Precharge all command - no parameter 0x2: Autorefresh command - no parameter 0x3: Enter deep-power-down - no parameter 0x4: Exit deep-power-down - no parameter 0x5: Enter self-refresh - no parameter 0x6: Exit self-refresh - no parameter 0x7: Set CKE signal high - no parameter 0x8: Set CKE low - no parameter 0x9: Reserved 0xA: Reserved 0xB: Reserved 0xC: Reserved Table 10-186. Register Call Summary for Register SDRC_MANUAL_p SDRAM Controller (SDRC) Subsystem • Refresh Management: [0] • Power-Saving Features: [1] • SDRC Power-Down Mode: [2] • Autorefresh Management: [3] • Manual Software Commands: [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] • Low-Power SDR/Mobile DDR Initialization Sequence: [14] • Memory Power Management: [15] • SDRC Register Summary: [16] 2312 Memory Subsystem SPRUGN4L–May 2010–Revised June 2011 Copyright © 2010–2011, Texas Instruments Incorporated
Device D2D OCM_ROM OCM_RAM ROM (32K bytes) -Boot code USB HS DAP OCM subsystem RAM (64K bytes) Public Version www.ti.com On-Chip Memory Subsystem 10.3 On-Chip Memory Subsystem 10.3.1 OCM Subsystem Overview The on-chip memory subsystem consists of two separate on-chip memory controllers, one connected to an on-chip ROM (OCM_ROM) and the other connected to an on-chip RAM (OCM_RAM). Each memory controller has its own dedicated interface to the L3 interconnect. Figure 10-78 is an overview of the OCM subsystem. Figure 10-78. OCM Subsystem Overview 2D/3D Display System graphics subsystem DMA MPU subsystem L3 interconnect IVA2 SDRAM controller subsystem SDRAM external memory Camera subsystem GPMC USB Flash ROM, NAND external memories Multiple L3 initiators (such as remote devices) have access to the RAM through 2D/3D graphics, the MPU subsystem, sDMA, the camera subsystem, the display subsystem, IVA2, and USB. ROM is used for direct boot code and boot from external NAND flash. SPRUGN4L–May 2010–Revised June 2011 Memory Subsystem Copyright © 2010–2011, Texas Instruments Incorporated Ocm-003 2313
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This chapter describes the memory s
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Device GPMC External device/ memory
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Public Version www.ti.com General-P
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1 GBytes 512 MBytes 256 MBytes 128
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] (co
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
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nCS nBE0/CLE nWE nADV/ALE CSONTIME=
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nCS nBE0/CLE nWE Public Version www
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Row 0 Row 1 Row 2 Row 3 Row 252 Row
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512 Bytes input Row 0 Row 1 Row 2 R
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M0 Manual mode Rd/Wr/ SW Mode Size0
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M1 M2 M3 M4 Per-sector spares Spare
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M9 Per-sector spares, separate ECC
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GPMC_FCLK nCS nBE0/CLE nOE/nRE nADV
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Device GPMC module A [27:17] A [16:
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FCLK CLK nADV nCS nOE A/D bus ClkAc
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FCLK nCS nADV nWE A/D bus AdvWrOffT
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Public Version www.ti.com SDRAM Con
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Device SDRAM controller subsystem R
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MUX1 System address 31 30 29 28 27
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MUX23 System address Address mappin
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Configuration register file Rotatio
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Level 0 Region 0 Public Version www
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OCP slave interface OCP slave port
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BANKALLOCATION = 0b00 BANKALLOCATIO
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Endianism CSnMUXCFG field SDRC.SDRC
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CLK CMD WRITE DQ DQS CLK CMD DQ DQS
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CLK_IN SIGNAL_IN MODEMAXDELAY Initi
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Page 167 and 168: 8 bits 32 bits Y0 U Y1 V P0 P1 16 b
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