Chapter 10 Memory Subsystem.pdf

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Request for transaction on group 1 occurs during transactions on group 0. Public Version SDRAM Controller (SDRC) Subsystem www.ti.com ....... Group 6 Group 0 Group 1 Group 2 Group 3 Group 7 Requests were present on group 0 and group 3. An arbitration decision occurs. Class 1 was granted the access. Class 1 Class 2 Class 0 10.2.6.2.3.3 Number of Service Mechanism. Figure 10-71. Example of EXTENDEDGRANT Mechanism Class 1 - group 0 is granted for three consecutive transactions. To service the other requests (pending or new incoming), wait until completion of these three transactions. Request for transaction on class 0 occurs during transactions on class 1 - group 0. The SMS_CLASS_ROTATIONm[4:0] NOFSERVICES field defines the number of consecutive transactions (from 1 to 31) the VRFB is granted. For more information on LRU policy and Number of Service, refer to Section 10.2.4.1.3. 10.2.6.2.4 How these Mechanisms Interact As described in the previous sections, the arbitration within the SMS module is based on several mechanisms giving even more importance to the arbitration. Wen we need to grant the access on a transaction boundary, we recall that the question we have to answer is: What will be the next request to be serviced, and for how long? Thus, the two important concepts regarding the SMS mode of operation are: • The arbitration decision: we choose the next request to be serviced and so we grant it the access to the external memory. • The arbitration granularity: depending on the mechanism used, we define the boundary of the transaction: how long do we keep the grant? Figure 10-72 describes the decision happening between classes. Figure 10-73 explains the priority between groups within Class 1. So far, the arbitration decision has taken place at class boundaries and within a class containing two groups. Figure 10-74 recalls the generic way to service and therefore prioritize the requests within a class. Finally, Figure 10-75 recalls mechanisms used to define the boundary of the transaction being serviced (how long do we keep the grant?). 2272 Memory Subsystem SPRUGN4L–May 2010–Revised June 2011 Copyright © 2010–2011, Texas Instruments Incorporated sdrc-028
No A Class 0 empty? Yes Class 1 empty and class 2 not empty ? No Class 2 empty and class 1 not empty ? No Class 1 not empty and class 2 not empty ? A: The arbitration decision No Class 0 Yes Yes Yes Public Version www.ti.com SDRAM Controller (SDRC) Subsystem Figure 10-72. Arbitration Between Classes PWM Arbitration C0 - C1 -C2 C0 - C2 -C1 SMS_INTERCLASS_ARBITER[7:0] CLASS1PRIO field: defines the number M of transactions dedicated to class 1. SMS_INTERCLASS_ARBITER[23:16] CLASS2PRIO field: defines the number N of transactions dedicated to class 2. Class 2 Class 1 Class 1 Class 2 C0 Win SPRUGN4L–May 2010–Revised June 2011 Memory Subsystem Copyright © 2010–2011, Texas Instruments Incorporated C2 Win C1 Win C1 Win C2 Win sdrc-029 2273
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This chapter describes the memory s
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Device GPMC External device/ memory
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Public Version www.ti.com General-P
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1 GBytes 512 MBytes 256 MBytes 128
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] (co
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
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nCS nBE0/CLE nWE nADV/ALE CSONTIME=
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nCS nBE0/CLE nWE Public Version www
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Row 0 Row 1 Row 2 Row 3 Row 252 Row
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512 Bytes input Row 0 Row 1 Row 2 R
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M0 Manual mode Rd/Wr/ SW Mode Size0
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M1 M2 M3 M4 Per-sector spares Spare
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M9 Per-sector spares, separate ECC
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GPMC_FCLK nCS nBE0/CLE nOE/nRE nADV
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Device GPMC module A [27:17] A [16:
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FCLK CLK nADV nCS nOE A/D bus ClkAc
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FCLK nCS nADV nWE A/D bus AdvWrOffT
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Public Version www.ti.com SDRAM Con
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Device SDRAM controller subsystem R
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MUX1 System address 31 30 29 28 27
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MUX23 System address Address mappin
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Configuration register file Rotatio
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