Chapter 10 Memory Subsystem.pdf

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Public Version SDRAM Controller (SDRC) Subsystem www.ti.com The SDRC has three modes of automatic internal clock-gating behavior when the interconnect interface is idle, that is. there are no outstanding active transactions in progress. These modes are controlled through the SDRC.SDRC_POWER_REG[5:4] CLKCTRL and SDRC.SDRC_POWER_REG[23:8] AUTOCOUNT fields. • Mode 0: The autoclock gating feature is disabled. No internal clock gating is performed in the SDRC in response to the detection of an idle state on the interconnect interface. • Mode 1: A 16-bit counter starts decrementing when an interconnect idle condition is detected. The counter start value is loaded from the AUTOCOUNT 16-bit field. When this counter times out, internal clock gating within the SDRC is enabled. • If an interconnect active command is received before the counter times out, or if an internal autorefresh request is issued, the procedure is aborted, the counter stops decrementing, and the request is serviced immediately. • Mode 2: This mode is similar to mode 1, but before the internal clock gating, the SDRC places the SDRAM into self-refresh mode and turns off the external SDRAM clock. This is the lowest power mode. To achieve maximum power savings, TI recommends the use of the PWDENA-, EXTCLKDIS-, and CLKCTRL-related features. Table 10-103 explains the different power-saving configurations that can be programmed with the SDRC.SDRC_POWER_REG[3] EXTCLKDIS, SDRC.SDRC_POWER_REG[2] PWDENA, and SDRC.SDRC_POWER_REG[5:4] CLKCTRL bits. Table 10-103. Dynamic Power Saving Configurations CLKCTRL EXTCLKDIS PWDENA CKE External SDRC CLK (1) SDRAM State Latency When Exiting Power Mode 0 0 0 Always high Always on Keep previous state 0 0 1 Low when no Always on Power-down Zero-latency penalty access 0 1 0 Always high Off when no access Keep previous state 0 1 1 Low when no Off when no access Power-down One cycle penalty access 1 0 0 Always high Always on Keep previous state 1 0 1 Low when no Always on Power-down Zero-latency penalty access 1 1 0 Always high Off when no access Keep previous state 1 1 1 Low when no Off when no access Power-down One cycle penalty access 2 0 0 Low when no Off when no access Enter self-refresh after access after AUTOCOUNT AUTOCOUNT expiration expiration 2 0 1 Low when no Off when no access Enter self-refresh after access after AUTOCOUNT AUTOCOUNT expiration expiration 2 1 0 Low when no Off when no access Enter self-refresh after access AUTOCOUNT expiration 2 1 1 Low when no Off when no access Enter self-refresh after access AUTOCOUNT expiration (1) EXTCLK can be set to 1 all the time for power optimization purposes, except when manual commands are sent. In this case, users must set EXTCLKDIS to 0 to ensure that a clock signal is provided to the memory device. NOTE: When connected to a DDR memory, the SDRC never gates the clock provided to the DLL components so that the DLL remains locked during these idle modes. This avoids the maximum of 500 clock cycles latency required for relocking the DLL when the DLL clock is switched off. 2240 Memory Subsystem SPRUGN4L–May 2010–Revised June 2011 Copyright © 2010–2011, Texas Instruments Incorporated
Public Version www.ti.com SDRAM Controller (SDRC) Subsystem All settings for the power-saving features are common to the two CSs. When two CSs are used, however, only the accessed CS exits self-refresh or deep-power-down mode. If the SDRC.SDRC_POWER_REG[6] SRFRONIDLEREQ bit is enabled, the SDRC enters self-refresh mode on a hardware idle request from the PRCM. The memory clock is automatically switched off, after which the SDRC sends an acknowledge back to the PRCM. In this situation, the power manager can switch the SDRC clock off. Therefore, if the SDRC is connected to a DDR memory, and if the DLL is enabled and in TrackingDelay mode, the SDRC waits for the lock status bit of the DLL to be asserted before accessing the memory when the system exits the idle state. The WAKEUPPROC bit of the SDRC_POWER_REG register enables the SDRC to automatically wait for 500 cycles (DLL relocking maximum time) before accessing the memory instead of using the LOCK signal. These 500 wait cycles are obeyed only when the DLL is set in TrackingDelay mode. For SDR mode and DLL ModeFixedDelay mode, the access is processed immediately. This mechanism is independent of the CLKCTRL field. NOTE: DLL Behavior Upon a Warm Reset Assertion: Upon a warm reset (the SDRC_DLLA_CTRL[3] ENADLL bit is not reset as it is not sensitive to warm reset but the DLL will be in unlock mode since DLL is reset. To lock the DLL again, theSDRC_DLLA_CTRL[3] ENADLL needs to be made 0 and then made 1 again. This will trigger a locking sequence. 10.2.4.4.9.3 Static Low-Power Operating Modes The software-driven controls for low-power operation modes include: • Possibility to put the memory in self-refresh using the manual command register (SDRC.SDRC_MANUAL_p (where p = 0 or 1 for SDRC CS0 or CS1). Each CS can be controlled independently. If both CSs are in self-refresh, the external SDRAM clock can be switched off by setting the SDRC.SDRC_POWER_REG[3] EXTCLKDIS control bit to 1. Self-refresh can be exited automatically if an access is initiated onto the CS. Only DPD must be exited manually. • Possibility to put the memory in deep-power-down mode, if supported by the SDRAM, using the manual command register. Each CS can be controlled independently. The external SDRAM clock can be switched off if both CSs are either in self-refresh or deep-power-down mode by setting the SDRC.SDRC_POWER_REG[3] EXTCLKDIS control bit to 1. Another manual command must be used for the memory to exit deep-power-down mode. After a memory exits from that mode all data are lost, and a full initialization sequence must be sent to the device, before it can be used. 10.2.4.4.10 SDRC Power-Down Mode In some applications, the SDRC power domain can be powered down while the external memory is in self-refresh mode. When the SDRC is powered off, an isolation stage prevents an unwanted exit from self-refresh when the context is restored. SDRC outputs that control the SDRAM are set to maintain self-refresh or deep-power-down (CKE low). When a reset occurs, the default reset state of the SDRC is power-down enable (PDE). When exiting the off mode: • Power is restored to the SDRC. • The software reconfigures all registers. If the NOMEMORYMRS bit is set, the MR and EMR registers can be set through the SDRC.SDRC_MR_p and SDRC.SDRC_EMR2_p registers (see Section 10.2.4.5, Mode Registers). • Exit from self-refresh mode is achieved through the SDRC.SDRC_MANUAL_p CMDCODE field. Because exit from the self-refresh field is unconditional (that is, the current state of the SDRC state-machine is not considered), ensure that autorefresh is disabled. Once the context is successfully restored, the software can reinitialize the SDRAM or return the SDRAM to self-refresh. When the device successfully exits self-refresh, autorefresh must be re-enabled. SPRUGN4L–May 2010–Revised June 2011 Memory Subsystem Copyright © 2010–2011, Texas Instruments Incorporated 2241
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This chapter describes the memory s
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Device GPMC External device/ memory
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Public Version www.ti.com General-P
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1 GBytes 512 MBytes 256 MBytes 128
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] (co
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
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nCS nBE0/CLE nWE nADV/ALE CSONTIME=
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nCS nBE0/CLE nWE Public Version www
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Row 0 Row 1 Row 2 Row 3 Row 252 Row
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512 Bytes input Row 0 Row 1 Row 2 R
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M0 Manual mode Rd/Wr/ SW Mode Size0
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M1 M2 M3 M4 Per-sector spares Spare
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M9 Per-sector spares, separate ECC
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GPMC_FCLK nCS nBE0/CLE nOE/nRE nADV
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Device GPMC module A [27:17] A [16:
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FCLK CLK nADV nCS nOE A/D bus ClkAc
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FCLK nCS nADV nWE A/D bus AdvWrOffT
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Device D2D OCM_ROM OCM_RAM ROM (32K
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Public Version www.ti.com On-Chip M
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