Chapter 10 Memory Subsystem.pdf

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www.ti.com SDRAM Controller (SDRC) Subsystem
Table 10-94. Register Call Summary for Register GPMC_BCH_SWDATA
General-Purpose Memory Controller
• GPMC Register Summary: [0]
10.2 SDRAM Controller (SDRC) Subsystem
This section describes the SDRAM controller (SDRC) subsystem.
10.2.1 SDRC Subsystem Overview
The SDRC subsystem module provides connectivity between the device POP-ed SDRAM memory
components. The module includes support for low-power double-data-rate SDRAM (LPDDR1).
The SDRC subsystem provides a high-performance interface to a variety of fast memory devices. It
comprises two submodules:
• The SDRAM memory scheduler (SMS), consisting of scheduler and virtual rotated frame-buffer (VRFB)
modules
• The SDRC
CAUTION
DDR SDRAM and SDR SDRAM memory types cannot be connected
simultaneously to the SDRC memory interface.
Figure 10-41 shows the SDRC subsystem environment.
SPRUGN4L–May 2010–Revised June 2011 Memory Subsystem
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