Chapter 10 Memory Subsystem.pdf

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Public Version General-Purpose Memory Controller www.ti.com 10.1.6.2.1 Supported Memories or Devices NAND flash and NOR flash architectures are the two flash technologies. The GPMC supports various types of external memory or device, basically any one that supports NAND or NOR protocols: • 8- and 16-bit width asynchronous or synchronous memory or device (8-bit: non burst device only) • 16-bit address and data multiplexed NOR flash devices (pSRAM, OneNAND) • 8- and 16-bit NAND flash device NOTE: Nonmultiplexed NOR flash devices are supported by the GPMC, but their use is highly limited. Because only ten address pins are available on the GPMC interface, the maximum device size supported is 2KB. 10.1.6.2.1.1 Memory Pin Multiplexing This section describes the interfacing differences of the supported GPMC memories. Table 10-24. Supported Memory Interfaces 16-Bit Address/Data Muxed Function OneNAND 16-bit NAND 8-bit NAND pSRAM or NOR Flash (1) gpmc_a11 A27 gpmc_a10 A26 gpmc_a9 A25 gpmc_a8 A24 gpmc_a7 A23 gpmc_a6 A22 gpmc_a5 A21 gpmc_a4 A20 gpmc_a3 A19 gpmc_a2 A18 gpmc_a1 A17 gpmc_d15 D15 or A16 IO15 gpmc_d14 D14 or A15 IO14 gpmc_d13 D13 or A14 IO13 gpmc_d12 D12 or A13 IO12 gpmc_d11 D11 or A12 IO11 gpmc_d10 D10 or A11 IO10 gpmc_d9 D9 or A10 IO9 gpmc_d8 D8 or A9 IO8 gpmc_d7 D7 or A8 IO7 gpmc_d6 D6 or A7 IO6 gpmc_d5 D5 or A6 IO5 gpmc_d4 D4 or A5 IO4 gpmc_d3 D3 or A4 IO3 gpmc_d2 D2 or A3 IO2 gpmc_d1 D1 or A2 IO1 gpmc_d0 D0 or A1 IO0 gpmc_clk CLK gpmc_ncs0 nCS0 (chip select) nCE0 (chip enable) gpmc_ncs1 nCS1 nCE1 gpmc_ncs2 nCS2 nCE2 (1) Addresses seen from the device side. When interfacing to the external IC, A1 is connected to the memory A0, A2 to the memory A1, and so on. 2174 Memory Subsystem SPRUGN4L–May 2010–Revised June 2011 Copyright © 2010–2011, Texas Instruments Incorporated
Public Version www.ti.com General-Purpose Memory Controller Table 10-24. Supported Memory Interfaces (continued) 16-Bit Address/Data Muxed Function OneNAND 16-bit NAND 8-bit NAND pSRAM or NOR Flash (1) GPMC_ncs3 nCS3 nCE3 GPMC_ncs4 nCS4 nCE4 GPMC_ncs5 nCS5 nCE5 GPMC_ncs6 nCS6 nCE6 GPMC_ncs7 nCS7 nCE7 gpmc_nadv_ale nADV (address valid) ALE (address latch enable) gpmc_noe nOE (output enable) nRE (read enable) gpmc_nwe nWE (write enable) nWE (write enable) gpmc_nbe0_cle nBE0 (byte enable) CLE (command latch enable) gpmc_nbe1 nBE1 gpmc_nwp nWP (write protect) nWP (write protect) gpmc_wait0 WAIT0 R/nB0 (ready/busy) gpmc_wait1 WAIT1 R/nB1 gpmc_wait2 WAIT2 R/nB2 gpmc_wait3 WAIT3 R/nB3 10.1.6.2.1.2 NAND Interface Protocol NAND flash architecture, introduced in 1989, is a flash technology. NAND is a page-oriented memory device (that is, read and write accesses are done by pages). NAND achieves density by sharing common areas of the storage transistor, which creates strings of serially connected transistors (in NOR devices, each transistor stands alone). Because of its high density, NAND is best suited to devices requiring high capacity data storage, such as pictures, music, or data files. Because of its nonvolatility, NAND is a good storage solution for many applications where mobility, low power, and speed are key factors. Low pin count and simple interface are other advantages of NAND. Table 10-25 summarizes the level of the NAND interface signals applied to external devices or memories. Table 10-25. NAND Interface Bus Operations Summary Bus operation CLE ALE nCE nWE (1) nRE (1) nWP Read (cmd input) H L L RE H x Read (add input) L H L RE H x Write (cmd input) H L L RE H H Write (add input) L H L RE H H Data input L L L RE H H Data output L L L H FE x Busy (during read) x x H (2) H (2) H (2) x Busy (during program) x x x x x H Busy (during erase) x x x x x H Write protect x x x x x L Stand-by x x H x x H/L (3) (1) RE stands for rising edge, FE stands for falling edge. (2) Can be either nCE high, or WE and nRE high (3) nWP must be biased to CMOS high or CMOS low for standby. 10.1.6.2.1.3 NOR Interface Protocol NOR flash architecture, introduced in 1988, is a flash technology. Unlike NAND, which is a sequential access device, NOR is directly addressable (that is, it is designed to be a random access device). NOR is best suited to devices used to store and run code or firmware, usually in small capacities. While NOR has fast read capabilities, it has slow write and erase functions compared to NAND architecture. SPRUGN4L–May 2010–Revised June 2011 Memory Subsystem Copyright © 2010–2011, Texas Instruments Incorporated 2175
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This chapter describes the memory s
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Device GPMC External device/ memory
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1 GBytes 512 MBytes 256 MBytes 128
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] (co
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] (co
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
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Page 55 and 56: 512 Bytes input Row 0 Row 1 Row 2 R
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Public Version www.ti.com SDRAM Con
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OCP slave interface OCP slave port
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BANKALLOCATION = 0b00 BANKALLOCATIO
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Endianism CSnMUXCFG field SDRC.SDRC
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CLK CMD WRITE DQ DQS CLK CMD DQ DQS
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CLK_IN SIGNAL_IN MODEMAXDELAY Initi
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8 bits 32 bits Y0 U Y1 V P0 P1 16 b
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Start configuration of VRFB context
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Initiator: Camera subsystem SDRC Su
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Request for transaction on class 1
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Class 1 and class 2 request for tra
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No A Class 0 empty? Yes Class 1 emp
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Status: There are n pending request
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4 GB 0x0000 0000 0x6C00 0000 0x6CFF
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Device D2D OCM_ROM OCM_RAM ROM (32K
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Public Version www.ti.com On-Chip M
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