Chapter 10 Memory Subsystem.pdf

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www.ti.com SDRAM Controller (SDRC) Subsystem
NOTE: As soon as the SDRC goes out of idle state, stalled accesses can be accepted and
processed:
• In SDR mode, the access can be immediately processed (unstalled).
• In DDR fixed delay mode, the accesses is processed (unstalled) after expiration of
MODEFIXEDDELAYINITLAT.
10.2.4.4.9 Power-Saving Features
In the SDRC there are three ways to save power and they can be applied simultaneously:
• Page opening/closure policy
• Dynamic low-power mode
• Static low-power mode
10.2.4.4.9.1 Page Opening/Closure Policy
The device supports only one page policy. The SDRC.SDRC_POWER_REG[0] PAGEPOLICY bit must be
set to 1.
The SDRC tracks open pages, if any, and determines whether the current access is to an open or a
closed page. If the accessed page is open, the SDRC executes the access immediately. The SDRC
performs the following procedure:
1. If the current page is already open on this bank the SDRC automatically issues a precharge command
to close that bank.
2. Opens the accessed page by issuing an active command to that bank
3. Executes the access by issuing a read or write command
Up to four pages can be open simultaneously with a limit of one page per bank. The pages remain open
until one of the following occurs:
• New read or write request to another page in the same bank
• Autorefresh request (a precharge all command is issued first)
• Self-refresh entry request (a precharge all command is issued first)
• Manual precharge all command
10.2.4.4.9.2 Dynamic Low-Power Operating Modes
The dynamic low-power operating modes of the SDRC are designed to:
• Control the external SDRAM clock(s)
• Control the internal clock gating of the SDRC when the interconnect interface is idle
• Control the self-refresh functionality
The external SDRAM is controlled through the SDRC.SDRC_POWER_REG[3] EXTCLKDIS and
SDRC.SDRC_POWER_REG[2] PWDENA bits. The EXTCLKDIS bit is used to disable the external clock
when no access is ongoing on the memory interface, whereas the PWDENA bit is used to activate the
power-down mode of the target memory by pulling the relevant CKE low each time the memory interface
is idle.
When the PWDENA bit is enabled but the EXTCLKDIS bit is not enabled, the SDRC still provides a
free-running clock to the external memories: clock gating is done internal to the memory component for
power savings.
EXTCLKDIS should be modified only when no access is in progress on the SDRAM interface. Software
control is required to make sure the interface is idle.
CKE is dynamically controlled based on the current memory command. There is a zero-latency penalty
when this mode is enabled.
SPRUGN4L–May 2010–Revised June 2011 Memory Subsystem
Copyright © 2010–2011, Texas Instruments Incorporated
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