Chapter 10 Memory Subsystem.pdf

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General-Purpose Memory Controller www.ti.com
• GPMC.GPMC_CONFIG1_i register settings:
– WRITEMULTIPLE bit at 1 (write multiple access)
– WRITETYPE bit at 1 (write synchronous)
– MUXADDDATA bit at 1 (address/data-multiplexed device)
When WRACCESSTIME completes, control-signal timings are frozen during the multiple data
transactions, corresponding to the PAGEBURSTACCESSTIME multiplied by the number of remaining
data transactions.
• Chip-select signal nCS:
– nCS assertion time is controlled by the GPMC.GPMC_CONFIG2_i[3:0] CSONTIME field and
ensures address setup time to nCS assertion.
– nCS deassertion time controlled by the GPMC.GPMC_CONFIG2_i[20:16] CSWROFFTIME field
and ensures address hold time to nCS deassertion.
• Address valid signal nADV:
– nADV assertion time is controlled by the GPMC.GPMC_CONFIG3_i[3:0] ADVONTIME field.
– nADV deassertion time is controlled by the GPMC.GPMC_CONFIG3_i[20:16] ADVWROFFTIME
field.
• Write enable signal nWE:
– nWE assertion indicates a write cycle.
– nWE assertion time is controlled by the GPMC.GPMC_CONFIG4_i[19:16] WEONTIME field.
– nWE deassertion time is controlled by the GPMC.GPMC_CONFIG4_i[28:24] WEOFFTIME field.
NOTE: The nWE falling edge must not be used to control the time when the burst first data is
driven in the address / data bus because some new devices require the nWE signal at
low during the address phase.
• First write data is driven by the GPMC at WRDATAONADMUXBUS (GPMC_CONFIG6_i[19:16]), when
in address/data mux configuration. The next write data of the burst is driven on the bus at
WRACCESSTIME + 1 during PAGEBURSTACCESSTIME GPMC_FCLK cycles. The last data of the
synchronous burst write is driven until WRCYCLETIME completes.
– WRACCESSTIME is defined in the GPMC.GPMC_CONFIG5_i register.
– The PAGEBURSTACCESSTIME parameter must be set accordingly with GPMCFCLKDIVIDER and
the memory-device internal configuration.
• Total access time (WRCYCLETIME) corresponds to WRACCESSTIME plus the address hold time
from nCS deassertion, plus time from WRACCESSTIME to CSWROFFTIME.
– WRCYCLETIME is defined in the GPMC.GPMC_CONFIG5_i register.
– In Figure 10-20, the WRCYCLETIME programmed value equals WRCYCLETIME0 +
WRCYCLETIME1.
• Direction signal DIR:
DIR is OUT during the entire access.
After a write operation, if no other access (read or write) is pending, the data bus keeps the previous
value. See Section 10.1.5.3.10, Bus Keeping Support.
Figure 10-21 shows the same synchronous burst write access when the chip-select is configured in
address/data-multiplexed mode.
2136 Memory Subsystem SPRUGN4L–May 2010–Revised June 2011
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