Chapter 10 Memory Subsystem.pdf
Chapter 10 Memory Subsystem.pdf
Chapter 10 Memory Subsystem.pdf
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Public Version<br />
www.ti.com General-Purpose <strong>Memory</strong> Controller<br />
to the WAITxEDGEDETECTIONSTATUS bit (x = 0 to 3) of the GPMC.GPMC_IRQSTATUS register<br />
according to the gpmc_wait pin used for the NAND device-ready signal monitoring. To detect a<br />
wait-to-no-wait transition, the transition detector requires a wait active time detection of a minimum of two<br />
GPMC_FCLK cycles. Software must incorporate precautions to clear the wait transition pin detector before<br />
wait (busy) time completes.<br />
A wait-to-no-wait transition detection can issue a GPMC interrupt if the WAITxEDGEDETECTIONENABLE<br />
bit in the GPMC.GPMC_IRQENABLE register is set and if the WAITxEDGEDETECTIONSTATUS bit field<br />
in the GPMC.GPMC_IRQSTATUS register is set.<br />
The WAITMONITORINGTIME field does not affect wait-to-no-wait transition time detection.<br />
It is also possible to poll the WAITxEDGEDETECTIONSTATUS bit field in the GPMC.GPMC_IRQSTATUS<br />
register according to the gpmc_wait pin used for the NAND device ready signal monitoring.<br />
<strong>10</strong>.1.5.14.3 ECC Calculator<br />
The general-purpose memory controller includes an error code correction (ECC) calculator circuitry that<br />
enables on-the-fly ECC calculation during data read or data program (that is, write) operations.<br />
The user can choose from two different algorithms with different error correction capabilities: Hamming<br />
code (for 1-bit error code correction), and BCH code (for 4- or 8-bit error correction) through the<br />
GPMC_ECC_CONFIG[16] ECCALGORITHM bit. Only one ECC context can be active at any given time<br />
through the GPMC_ECC_CONFIG[3:1] ECCCS bit. Even if two CSs use different ECC algorithms, one the<br />
Hamming code and the other a BCH code, they must define separate ECC contexts, because some of the<br />
ECC registers are common to all types of algorithms.<br />
<strong>10</strong>.1.5.14.3.1 Hamming Code<br />
All references to ECC in this section refer to the 1-bit error correction Hamming code.<br />
The ECC is based on a two-dimensional (row and column) bit parity accumulation known as Hamming<br />
code. The parity accumulation is done for a programmed number of bytes or Word16 read from the<br />
memory device or written to the memory device in stream mode.<br />
There is no automatic error detection or correction, and it is the software NAND driver responsibility to<br />
read the multiple ECC calculation results, compare them to the expected code value, and take the<br />
appropriate corrective actions according to the error handling strategy (ECC storage in spare byte, error<br />
correction on read, block invalidation).<br />
The ECC engine includes a single accumulation context. It can be allocated to a single designated<br />
chip-select at a time and parallel computations on different chip-selects are not possible. Since it is<br />
allocated to a single chip-select, the ECC computation is not affected by interleaved GPMC accesses to<br />
other chip-selects and devices. The ECC accumulation is sequentially processed in the order of data read<br />
from or written to the memory on the designated chip-select. The ECC engine does not differentiate read<br />
accesses from write accesses and does not differentiate data from command or status information. It is<br />
the software responsibility to make sure only relevant data are passed to the NAND flash memory while<br />
the ECC computation engine is active.<br />
The starting NAND page location must be programmed first, followed by an ECC accumulation context<br />
reset with an ECC enabling, if required. The NAND device accesses discussed in the following sections<br />
must be limited to data read or write until the specified number of ECC calculations is completed.<br />
<strong>10</strong>.1.5.14.3.1.1 ECC Result Register and ECC Computation Accumulation Size<br />
The GPMC includes up to nine ECC result registers (GPMC.GPMC_ECCj_RESULT, j = 1 to 9) to store<br />
ECC computation results when the specified number of bytes or Word16s has been computed.<br />
The ECC result registers are used sequentially; one ECC result is stored in one ECC result register on the<br />
list, the next ECC result is stored in the next ECC result register on the list, and so forth, until the last ECC<br />
computation. The GPMC.GPMC_ECCj_RESULT register value is valid only when the programmed<br />
number of bytes or Word16s has been accumulated, which means that the same number of bytes or<br />
Word16s has been read from or written to the NAND device in sequence.<br />
SPRUGN4L–May 20<strong>10</strong>–Revised June 2011 <strong>Memory</strong> <strong>Subsystem</strong><br />
Copyright © 20<strong>10</strong>–2011, Texas Instruments Incorporated<br />
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