Chapter 10 Memory Subsystem.pdf

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10.2.5.3.1 Chip-Select Configuration
CS0 always starts at 0x8000 0000 (with respect to the 32-bit interconnect address). There is no restriction
on the presence of any SDRAM on CS0 or CS1.
The total address space of the SDRC is 1G byte/8G bits. The total address space is divided into 8 *
128M-byte partitions as shown in Figure 10-51. Each partition is a possible start address for CS1, except
for the partition occupied by CS0.
The start address for CS1 is defined by the SDRC.SDRC_CS_CFG[9:8] CS1STARTLOW and
SDRC.SDRC_CS_CFG[3:0] CS1STARTHIGH fields.
Space 0, selected by the SDRC using the CS0 (nCS0) output pin, is always at offset 0 from the SDRAM
memory space base address. The size of this area is programmable through the
SDRC.SDRC_MCFG_p[17:8] RAMSIZE field, where p = 0. Space 1, selected by the SDRC using the CS1
(nCS1) output pin, is at an offset from the SDRAM memory space base address; this offset is
programmable in 128M-byte increments. The size of this area is programmable through the
SDRC.SDRC_MCFG_p[17:8] RAMSIZE field, where p = 1. The type of device for each area is
programmable through the SDRC.SDRC_MCFG_p register (where p = 0 or 1 for SDRC CS0 or CS1).
NOTE: Ensure that space 0 and space 1 do not overlap each other or extend farther than the
maximum 1G-byte SDRC memory space, as explained in Section 2.2, Global Memory Space
Mapping, of Chapter 2, Memory Mapping.
10.2.5.3.2 Memory Configuration
The memory configuration is defined on a per-CS basis through the SDRC.SDRC_MCFG_p register
(where p = 0 or 1 for SDRC CS0 or CS1).
Table 10-104 lists the memory configuration.
Bit Field Comments
ADDRMUXLEGACY Address multiplexing scheme
Table 10-104. Memory Configuration
RAMSIZE Defines the physical RAM address space in terms of 2M -byte chunks
B32NOT16 External device data bus width.
DEEPPD Set this bit if the memory supports deep-power-down mode. (This bit is only a flag for software. It
does not affect any SDRC function.)
DDRTYPE Mobile DDR
RAMTYPE Single Data Rate or Double Data Rate SDRAM
NOTE: Exported Register Reset Values and Lock Bit
The reset values of SDRC.SDRC_MCFG_p and SDRC.SDRC_SHARING are exported in the
control module. At reset, these registers take the value previously stored in the control
module. A new bit is added to each register to provide the capability to lock these three
registers into read-only accesses:
• SDRC.SDRC_MCFG_p[30] LOCKSTATUS bit (p = 0 or 1 for CS0 or CS1)
• SDRC.SDRC_SHARING[30] LOCK bit
The reset value of each lock bit is also imported from the control module.
10.2.5.3.3 SDRAM AC Timing Parameters
The AC parameters described in Table 10-105 can be independently programmed (standard JEDEC
LPDDR1 terminology is used here) in clock cycles for each of the two memory areas through registers
SDRC.SDRC_ACTIM_CTRLA_p and SDRC.SDRC_ACTIM_CTRLB_p (p = 0 or 1, depending on the CS
area).
2250 Memory Subsystem SPRUGN4L–May 2010–Revised June 2011
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