Chapter 10 Memory Subsystem.pdf

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www.ti.com SDRAM Controller (SDRC) Subsystem
Bits Field Name Description Type Reset
31:18 RESERVED Write 0s for future compatibility RW 0x00000
Reads return zeros.
17:16 TWTR Internal write to read command delay. RW 0x0
0x0: 1 minimum clock cycle before next command
0x1: 1 minimum clock cycle
0x2: 2 minimum clock cycles
0x3: 3 minimum clock cycles
15 RESERVED Write 0s for future compatibility RW 0
Reads return zeros.
14:12 TCKE CKE minimum pulse width (high and low) RW 0x0
0x0: 1 minimum clock cycle
0x1: 1 minimum clock cycle
0x2: 2 minimum clock cycles
...
0x7: 7 minimum clock cycles
11 RESERVED Write 0s for future compatibility RW 0
Reads return zeros.
10:8 TXP Exit power-down to next valid command delay. RW 0x0
0x0: 1 minimum clock cycle before next command
0x1: 1 minimum clock cycle
0x2: 2 minimum clock cycles
...
0x7: 7 minimum clock cycles
7:0 TXSR Self-refresh exit to active period RW 0x00
Table 10-182. Register Call Summary for Register SDRC_ACTIM_CTRLB_p
SDRAM Controller (SDRC) Subsystem
• SDRAM AC Timing Parameters: [0]
• SDRC Register Summary: [1]
Table 10-183. SDRC_RFR_CTRL_p
Address Offset 0x0000 00A4 + (0x0000 0030 * p) Index p = 0 to 1
Physical Address 0x6D00 00A4 + (0x0000 0030 * p) Instance SDRC
Description SDRAM memory autorefresh control
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED ARCV RESERVED ARE
Bits Field Name Description Type Reset
31:24 RESERVED Write 0s for future compatibility. Read returns 0. RW 0x00
23:8 ARCV Autorefresh counter value to set the refresh period. The autorefresh RW 0x0000
counter is uploaded with the result of:
(tREFI / tCK) - 50
7:2 RESERVED Write 0s for future compatibility. Read returns 0. RW 0x00
1:0 ARE Autorefresh enable RW 0x0
0x0: Autorefresh is disabled
0x1: Counter is loaded with ARCV: 1 autorefresh command when
autorefresh counter reaches 0.
0x2: Counter is loaded with 4 * ARCV: Burst of 4 autorefresh commands
when autorefresh counter reaches 0.
0x3: Counter is loaded with 8 * ARCV: Burst of 8 autorefresh commands
when autorefresh counter reaches 0.
SPRUGN4L–May 2010–Revised June 2011 Memory Subsystem
Copyright © 2010–2011, Texas Instruments Incorporated
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