Chapter 10 Memory Subsystem.pdf

Public Version
www.ti.com General-Purpose Memory Controller
Bits Field Name Description Type Reset
2 DMAMODE Selects interrupt synchronization or DMA request RW 0x0
synchronization
0x0: Interrupt synchronization is enabled. Only interrupt
line will be activated on FIFO threshold crossing.
0x1: DMA request synchronization is enabled. A DMA
request protocol is used.
1 RESERVED Write 0s for future compatibility. Read returns 0. RW 0x0
0 ACCESSMODE Selects pre-fetch read or write-posting accesses RW 0x0
0x0: Pre-fetch read mode
0x1: Write-posting mode
Table 10-70. Register Call Summary for Register GPMC_PREFETCH_CONFIG1
General-Purpose Memory Controller
• NAND Device Basic Programming Model: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20]
[21] [22] [23] [24] [25] [26] [27] [28] [29] [30] [31]
• GPMC Register Summary: [32]
Address Offset 0x0000 01E4
Table 10-71. GPMC_PREFETCH_CONFIG2
Physical Address 0x6E00 01E4 Instance GPMC
Description Prefetch engine configuration 2
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED TRANSFERCOUNT
Bits Field Name Description Type Reset
31:14 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x00000
13:0 TRANSFERCOUNT Selects the number of bytes to be read or written by the engine RW 0x0000
to the selected CS
0x0000: 0 byte
0x0001: 1 byte
...
0x2000: 8 Kbytes
Table 10-72. Register Call Summary for Register GPMC_PREFETCH_CONFIG2
General-Purpose Memory Controller
• NAND Device Basic Programming Model: [0] [1] [2] [3]
• GPMC Register Summary: [4]
Address Offset 0x0000 01EC
Table 10-73. GPMC_PREFETCH_CONTROL
Physical Address 0x6E00 01EC Instance GPMC
Description Prefetch engine control
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
SPRUGN4L–May 2010–Revised June 2011 Memory Subsystem
Copyright © 2010–2011, Texas Instruments Incorporated
STARTENGINE
2197