Bulletin 2012/02 - European Patent Office
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Bulletin 2012/02 - European Patent Office

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(H01L) II.1(1)<br />

H01L 21/762 → (51) H01L 21/316<br />

H01L 21/762 → (51) H01L 21/764<br />

(51) H01L 21/764 (11) 1 427 010 B1<br />

H01L 21/3063 H01L 21/762<br />

H01L 29/06 B81B 1/00<br />

B81C 1/00 B81B 3/00<br />

(25) It (26) En<br />

(21) <strong>02</strong>425742.0 (22) 29.11.20<strong>02</strong><br />

(84) DE FR GB IT<br />

(43) 09.06.2004<br />

(54) • Verfahren zur Herstellung eines Halbleitersubstrates<br />

mit mindestens einem vergrabenen<br />

Hohlraum<br />

• Manufacturing method of a semiconductor<br />

substrate comprising at least a buried<br />

cavity<br />

• Procédé de fabrication d'un substrat<br />

semiconducteur comprenant au moins une<br />

cavité enterrée<br />

(73) STMicroelectronics Srl, Via Olivetti 2, 20041<br />

Agrate Brianza (MB), IT<br />

(72) Renna, Crocifisso Marco Antonio, 93012<br />

Gela (Caltanisetta), IT<br />

La Magna, Luigi, 95048 Scordia (Catania), IT<br />

Lorenti, Simona, 95129 Catania, IT<br />

Coffa, Salvatore, 95030 Tremestieri Etneo<br />

(Catania), IT<br />

(74) Botti, Mario, et al, Botti & Ferrari S.r.l. Via<br />

Cappellini, 11, <strong>2012</strong>4 Milano, IT<br />

(60) 10184095.7 / 2 280 412<br />

(51) H01L 21/768 (11) 1 610 377 B1<br />

H01L 21/288<br />

(25) En (26) En<br />

(21) 05075796.2 (22) 07.04.2005<br />

(84) AT BE BG CH CY CZ DE DK EE ES FI FR GB<br />

GR HU IE IS IT LI LT LU MC NL PL PT RO SE<br />

SI SK TR<br />

(43) 28.12.2005<br />

(30) 13.04.2004 US 561701 P<br />

16.03.2005 US 81934<br />

(54) • System zum Modifizieren kleiner Strukturen<br />

• System for modifying small structures<br />

• Système pour modifier des petites structures<br />

(73) FEI COMPANY, 5350 NE Dawson Creek<br />

Drive, Hillsboro, Oregon 97124-5793, US<br />

(72) Gu, George Y., Burlington 01803 Massachusetts,<br />

US<br />

Bassom, Neil J., Hamilton 01928 Massachusetts,<br />

US<br />

Gannon, Thomas J., West Newbury 01985<br />

Massachusetts, US<br />

Liu, Kun, Peabody 01960 Massachusetts, US<br />

(74) Bakker, Hendrik, et al, FEI Company <strong>Patent</strong><br />

Department P.O. Box 1745, 56<strong>02</strong> BS Eindhoven,<br />

NL<br />

(51) H01L 21/78 (11) 1 659 624 B1<br />

H01L 21/00 H01L 21/683<br />

(25) En (26) En<br />

(21) 060<strong>02</strong>977.4 (22) 20.11.2003<br />

(84) DE<br />

(43) 24.05.2006<br />

(30) 20.11.20<strong>02</strong> JP 20<strong>02</strong>336415<br />

20.11.20<strong>02</strong> JP 20<strong>02</strong>336416<br />

(54) • Verfahren zum Herstellen einer Halbleiteranordnung<br />

• Method of manufacturing a semiconductor<br />

device<br />

• Procédé de fabrication d'un dispositif<br />

semi-conducteur<br />

(73) Panasonic Corporation, 1006, Oaza Kadoma,<br />

Kadoma-shi Osaka 571-8501, JP<br />

(72) Arita, Kiyoshi, Munakata-gun Fukuoka 811-<br />

3225, JP<br />

Europäisches <strong>Patent</strong>blatt<br />

<strong>European</strong> <strong>Patent</strong> <strong>Bulletin</strong><br />

<strong>Bulletin</strong> européen des brevets<br />

(74) Grünecker, Kinkeldey, Stockmair & Schwanhäusser,<br />

Anwaltssozietät Leopoldstrasse 4,<br />

808<strong>02</strong> München, DE<br />

(62) 03774103.0 / 1 563 535<br />

(51) H01L 21/822 (11) 2 200 078 B1<br />

H01L 27/04<br />

(25) Ja (26) En<br />

(21) 07829443.6 (22) 09.10.2007<br />

(84) AT BE BG CH CY CZ DE DK EE ES FI FR GB<br />

GR HU IE IS IT LI LT LU LV MC MT NL PL PT<br />

RO SE SI SK TR<br />

(43) 23.06.2010<br />

(86) JP 2007/069705 09.10.2007<br />

(87) WO 2009/047840 2009/16 16.04.2009<br />

(54) • INTEGRIERTES HALBLEITERSCHAL-<br />

TUNGSBAUELEMENT<br />

• SEMICONDUCTOR INTEGRATED CIRCUIT<br />

DEVICE<br />

• DISPOSITIF DE CIRCUIT INTEGRE SEMI-<br />

CONDUCTEUR<br />

(73) Fujitsu Limited, 1-1, Kamikodanaka 4-chome<br />

Nakahara-ku, Kawasaki-shi, Kanagawa 211-<br />

8588, JP<br />

(72) SOSOGI, Yasuhide, Kawasaki-shi Kanagawa<br />

211-8588, JP<br />

(74) Lewin, David Nicholas, Haseltine Lake LLP<br />

Lincoln House, 5th Floor 300 High Holborn,<br />

London WC1V 7JH, GB<br />

H01L 21/8246 → (51) H01L 27/112<br />

H01L 21/8247 → (51) H01L 27/112<br />

(51) H01L 23/00 (11) 1 480 267 B1<br />

(25) En (26) En<br />

(21) 04003767.3 (22) 19.<strong>02</strong>.2004<br />

(84) AT BE BG CH CY CZ DE DK EE ES FI FR GB<br />

GR HU IE IT LI LU MC NL PT RO SE SI SK<br />

TR<br />

(43) 24.11.2004<br />

(30) 23.05.2003 JP 2003146550<br />

(54) • Integrierte Elektronikkomponente<br />

• Integrated electronic component<br />

• Composant électronique intégré<br />

(73) MURATA MANUFACTURING CO., LTD., 10-<br />

1, Higashikotari 1-chome, Nagaokakyo-shi,<br />

Kyoto 617-8555, JP<br />

(72) Ogawa, Keiji, Murata Manufacturing Co.,<br />

Ltd., Nagaokakyo-shi Kyoto-fu 617-8555, JP<br />

Kato, Mitsuhide , Murata Manufacturing Co.,<br />

Ltd., Nagaokakyo-shi Kyoto-fu 617-8555, JP<br />

Yamada, Yoshinori, Murata Manufacturing<br />

Co., Ltd., Nagaokakyo-shi Kyoto-fu 617-<br />

8555, JP<br />

(74) Schoppe, Fritz, Schoppe, Zimmermann,<br />

Stöckeler & Zinkler <strong>Patent</strong>anwälte Postfach<br />

246, 82043 Pullach bei München, DE<br />

H01L 23/12 → (51) H05K 1/11<br />

H01L 23/29 → (51) C08G 77/56<br />

(51) H01L 23/485 (11) 1 754 256 B1<br />

H01L 23/58 H01L 23/498<br />

(25) En (26) En<br />

(21) 05747294.6 (22) 18.05.2005<br />

(84) AT BE BG CH CY CZ DE DK EE ES FI FR GB<br />

GR HU IE IS IT LI LT LU MC NL PL PT RO SE<br />

SI SK TR<br />

AL BA HR LV MK YU<br />

(43) 21.<strong>02</strong>.2007<br />

(86) IB 2005/051613 18.05.2005<br />

(87) WO 2005/117109 2005/49 08.12.2005<br />

(30) 28.05.2004 EP 041<strong>02</strong>408<br />

(54) • CHIP MIT ZWEI GRUPPEN VON CHIP-<br />

KONTAKTEN<br />

636<br />

<strong>Patent</strong>e<br />

<strong>Patent</strong>s<br />

Brevets (<strong>02</strong>/<strong>2012</strong>) 11.01.<strong>2012</strong><br />

• CHIP HAVING TWO GROUPS OF CHIP<br />

CONTACTS<br />

• PUCE COMPRENANT DEUX GROUPES DE<br />

CONTACTS<br />

(73) NXP B.V., High Tech Campus 60, 5656 AG<br />

Eindhoven, NL<br />

(72) SCHEUCHER, Heimo, A-1101 Vienna, AT<br />

(74) Krott, Michel, et al, NXP Semiconductors IP<br />

& Licensing Department High Tech Campus,<br />

5656 AE Eindhoven, NL<br />

(51) H01L 23/498 (11) 1 564 811 B1<br />

(25) En (26) En<br />

(21) 05075241.9 (22) 31.01.2005<br />

(84) AT BE BG CH CY CZ DE DK EE ES FI FR GB<br />

GR HU IE IS IT LI LT LU MC NL PL PT RO SE<br />

SI SK TR<br />

(43) 17.08.2005<br />

(30) 17.<strong>02</strong>.2004 US 780163<br />

(54) • Verpackung für eine integrierte Schaltung<br />

mit je einem Substrat auf beiden Seiten<br />

und mit einem Leiterrahmen der Leiter mit<br />

erhöhter Dicke aufweist<br />

• Dual-sided substrate integrated circuit<br />

package including a leadframe having leads<br />

with increased thickness<br />

• Boîtier de circuit intégré avec substrat sur<br />

chacune de ses deux faces comportant un<br />

cadre de connexion avec des conducteurs<br />

à épaisseur augmentée<br />

(73) Delphi Technologies, Inc., PO Box 5052,<br />

Troy, MI 48007, US<br />

(72) Mock, Roger A., Kokomo, IN 469<strong>02</strong>, US<br />

Gerbsch, Erich W., Cicero, IN 46034, US<br />

(74) Denton, Michael John, et al, Delphi France<br />

SAS 64 Avenue de la Plaine de France ZAC<br />

Paris Nord II B.P. 65059, Tremblay en<br />

France, 95972 Roissy Charles de Gaulle<br />

Cedex, FR<br />

H01L 23/498 → (51) H01L 23/485<br />

(51) H01L 23/525 (11) 1 309 0<strong>02</strong> B1<br />

(25) En (26) En<br />

(21) <strong>02</strong><strong>02</strong>4929.8 (22) 06.11.20<strong>02</strong><br />

(84) DE FR GB<br />

(43) 07.05.2003<br />

(30) 06.11.2001 JP 2001340872<br />

(54) • Halbleiteranordnung mit einer Sicherung<br />

und ihr Herstellungsverfahren<br />

• Semiconductor device having fuse and its<br />

manufacturing method<br />

• Dispositif semi-conducteur ayant un fusible<br />

et son procédé de fabrication<br />

(73) YAMAHA CORPORATION, 10-1 Nakazawacho<br />

Naka-ku, Hamamatsu-shi Shizuoka-ken,<br />

JP<br />

(72) Kamiya, Takayuki, Hamamatsu-shi, Shizuoka-ken,<br />

JP<br />

Omura, Masayoshi, Hamamatsu-shi, Shizuoka-ken,<br />

JP<br />

(74) Emde, Eric, et al, Wagner & Geyer Gewürzmühlstrasse<br />

5, 80538 München, DE<br />

(51) H01L 23/538 (11) 2 <strong>02</strong>7 600 B1<br />

(25) De (26) De<br />

(21) 07701291.2 (22) 01.<strong>02</strong>.2007<br />

(84) AT BE BG CH CY CZ DE DK EE ES FI FR GB<br />

GR HU IE IS IT LI LT LU LV MC NL PL PT RO<br />

SE SI SK TR<br />

(43) 25.<strong>02</strong>.2009<br />

(86) AT 2007/000045 01.<strong>02</strong>.2007<br />

(87) WO 2007/087660 2007/32 09.08.2007<br />

(30) <strong>02</strong>.<strong>02</strong>.2006 AT 16<strong>02</strong>006<br />

(54) • Verfahren zum Einbetten zumindest eines<br />

Bauelements in einem Leiterplattenelement<br />

• Method for embedding at least one component<br />

in a printed circuit board element

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