Geode GXLV Processor Series Low Power Integrated x86 Solutions

Geode GXLV Processor SeriesIntegrated Functions (Continued)4.1.4 Scratchpad RAMTo improve software performance for specific applications,part of the L1 cache (2, 3, or 4 KB) can be programed tooperate as a scratchpad RAM. This scratchpad RAMoperates at L1 speed which can speed up time-criticalsoftware operations. The scratchpad RAM is taken fromset 0 of the L1 cache. Setting aside this RAM makes theL1 cache smaller by the scratchpad RAM size. Thescratchpad RAM size is controlled by bits in the GCR register(Index B8h, bits[3:2]). See Table 4-1 on page 97.The scratchpad RAM is usually memory mapped by BIOSto the upper memory region defined by the GCR register(Index B8h, bits [1:0]). Once enabled, the valid bits for thescratchpad RAM will always be true and the scratchpadRAM locations will never be flushed to external memory.The scratchpad RAM serves as a general purpose highspeed RAM and as a BLT buffer for the graphics pipeline.4.1.4.1 Initialization of Scratchpad RAMThe scratchpad RAM must be initialized before the L1cache is enabled. To initialize the scratchpad RAM after acold boot:1) Initialize the tags of the scratchpad RAM using thetest registers TR4 and TR5 as outlined in Section3.3.2.4 “TLB Test Registers”. The tags are normallyprogrammed with an address value equivalent toGX_BASE (GCR register).2) Enable the scratchpad RAM to the desired size (GCRregister). This action will also lock down the tags.3) Enable the L1 cache. Section 3.3.2.1 “Control Registers”.4.1.4.2 Scratchpad RAM UtilizationUse of scratchpad RAM by applications and drivers mustbe tightly controlled. To avoid conflicts, application softwareand third-party drivers should generally avoidaccesses to the scratchpad RAM area. The scratchpadRAM is used by the graphics pipeline BLT buffers, andNational-supplied display drivers and virtualization software.Table 4-3 describes the 2 KB, 3 KB, and 4 KBscratchpad RAM organization used by National developedsoftware. The BLT buffers are programmed usingCPU_READ/CPU_WRITE instructions described in Section4.1.6 on page 102. If the graphics pipeline or Nationalsoftware is used, and it is desirable to use scratchpadRAM by software other than that supplied by National,please contact your local National Semiconductor technicalsupport representative.4.1.4.3 BLT BufferAddress registers, BitBLT, have been added to the frontend of the L1 cache to enable the graphics pipeline todirectly access a portion of the scratchpad RAM as a BLTbuffer. Table 4-4 summarizes these registers. These registersdo not have default values and must be initializedbefore use. Table 4-5 gives the register/bit formats. A 16-byte line buffer dedicated to the graphics pipeline BLToperations has been added to minimize accesses to theL1 cache.When the BLT operation begins, the graphics pipelinegenerates a 32 bit data BLT request to the L1 cache. Thisrequest goes through the BitBLT registers to produce anaddress into the scratchpad RAM. TheL1_BBx_POINTER register automatically incrementsafter each access. A BLT operation generates manyaccesses to the BLT buffer to complete a BLT transfer. Atthe end of the BLT operation the graphics pipeline generatesa signal to reload the L1_BBx_POINTER registerwith the L1_BBx_BASE register. This allows the BLTbuffertobeusedoverandoveragainwithaminimumofsoftware overhead.See Section 4.4 “Graphics Pipeline” on page 125 on programmingthe graphics pipeline to generate a BLT.Table 4-3. Scratchpad Organization2 KB Configuration 3 KB Configuration 4 KB ConfigurationOffset Size Offset Size Offset Size DescriptionGX_BASE + 0EE0h 288 bytes GX_BASE + 0EE0h 288 bytes GX_BASE + 0EE0h 288 bytes SMM scratchpadGX_BASE + 0E60h 128 bytes GX_BASE + 0E60h 128 bytes GX_BASE + 0E60h 128 bytes Driver scratchpadGX_BASE + 0800h 816 bytes GX_BASE + 0400h 1328 bytes GX_BASE + 0h 1840 bytes BLT Buffer 0GX_BASE + 0B30h 816 bytes GX_BASE + 0930h 1328 bytes GX_BASE + 730h 1840 bytes BLT Buffer 1www.national.com 100 Revision 1.3