Geode GXLV Processor Series Low Power Integrated x86 Solutions

Geode GXLV Processor SeriesIntegrated Functions (Continued)4.3.1 Memory Array ConfigurationThe memory controller supports up to four 64-bit SDRAMbanks, with maximum of eight physical devices per bank.Banks 0:1 and 2:3 must be identical configurations. Two168-pin unbuffered SDRAM modules (DIMM) satisfythese requirements Though the following discussion isDIMM centric, DIMMs are not a system requirement. EachDIMM receives a unique set of RAS, CAS, WE, and CKElines. Each DIMM can have one or two 64-bit DIMMbanks. Each DIMM bank is selected by a unique chipselect (CS). There are four chip select signals to choosebetween a total of four DIMM banks. Each DIMM bankalso receives a unique SDCLK. Each DIMM bank canhave two or four component banks. Component bankselection is done through the bank address (BA) lines.For example, 16-Mbit SDRAM have two component banksand 64-Mbit SDRAM have two or four component banks.For single DIMM bank modules, the memory controllercan support two DIMMS with a maximum of eight componentbanks. For dual DIMM bank modules, the memorycontroller can support two DIMMs with a maximum of 16componentbanks.Upto16bankscanbeopenatthesame time. Refer to the SDRAM manufacturer’s specificationfor more information on component banks.Geode GXLVProcessorMA[12:0]BA[1:0]MD[63:0]DQM[7:0]RASA#CASA#WEA#CS0#CS1#CKEASDCLK0SDCLK1RASB#CASB#WEB#CS2#CS3#CKEBSDCLK2SDCLK3Bank 0 Bank 1A[12:0]BA[1:0]MD[63:0]DQM[7:0]RAS#CAS#WE#S0#, S2#CKE0CK0, CK2A[12:0]BA[1:0]MD[63:0]DQM[7:0]RAS#CAS#WE#S0#, S2#CKE0CK0, CK2DIMM 0DIMM 1A[12:0]BA[1:0]MD[63:0]DQM[7:0]RAS#CAS#WE#S1#, S3#CKE1CK1, CK3Bank 0 Bank 1A[12:0]BA[1:0]MD[63:0]DQM[7:0]RAS#CAS#WE#S1#, S3#CKE1CK1, CK3Figure 4-4. Memory Array Configurationwww.national.com 108 Revision 1.3