Geode GXLV Processor Series Low Power Integrated x86 Solutions

Geode GXLV Processor SeriesIntegrated Functions (Continued)Table 4-38. Virtual VGA Register Summary4.6.4 Virtual VGA Register DescriptionsThis section describes the registers contained in thegraphics pipeline used for VGA emulation. The graphicspipeline maps 200h locations starting atGX_BASE+8100h. Refer to Section 4.1.2 “Control Registers”on page 99 for instructions on accessing these registers.The registers are summarized in Table 4-38, followed bydetailed bit formats in Table 4-39.GX_BASE+Memory Offset Type Name/Function Default Value8140h-8143h R/W GP_VGA_WRITEGraphics Pipeline VGA Write Patch Control Register: Controls the VGA memorywrite path in the graphics pipeline.xxxxxxxxh8144h-8147h R/W GP_VGA_READGraphics Pipeline VGA Read Patch Control Register: Controls the VGA memoryread path in the graphics pipeline.8210h-8213h R/W GP_VGA_BASE VGAGraphics Pipeline VGA Memory Base Address Register: Specifies the offset ofthe VGA memory, starting from the base of graphics memory.8214h-8217h R/W GP_VGA_LATCHGraphics Pipeline VGA Display Latch Register: Provides a memory mappedway to read or write the VGA display latch.00000000hxxxxxxxxhxxxxxxxxhwww.national.com 164 Revision 1.3