Geode GXLV Processor Series Low Power Integrated x86 Solutions

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Geode GXLV Processor SeriesIntegrated Functions (Continued)Table 4-10. Region-Control-Field Bit DefinitionsBitPosition Function3 PCI Accessible: The PCI slave can access this memory if this bit is set high and if the appropriate Read or Write Enablebit is also set high.2 Cache Enable: Caching this region of memory is inhibited if this bit is cleared.1 Write Enable: Write operations to this region of memory are allowed if this bit is set high. If this bit is cleared, then writeoperations in this region are directed to the PCI master.0 Read Enable: Read operations to this region of memory are allowed if this bit is set high. If this bit is cleared then readoperations in this region are directed to the PCI master.Note: If Cache Enable = 1 and Write Enable = 1, the Write Enable determination occurs after the data has passed the cache. Sincethe cache does write update, write data will change the cache if the address is cached. If a read then occurs to that address,the data will come from the written data that is in the cache even though the address is not writable. If this must be avoidedthen do not make the region cacheable.www.national.com 106 Revision 1.3
Integrated Functions (Continued)4.3 MEMORY CONTROLLERThe memory controller arbitrates requests from the X-Bus(processor and PCI), display controller, and graphics pipeline.The GXLV processor supports LVTTL (low voltage TTL)technology. LVTTL technology allows the SDRAM interfaceof the memory controller to run at frequencies up to100 MHz.The SDRAM clock is a function of the core clock. TheSDRAM bus can be run at speeds that range between 66Processor/PCIControlDisplay ControllerControlGraphics PipelineControlProcessor/PCI I/FDisplay Controller I/FGraphics Pipeline I/FRFSHArbiterMHz and 100 MHz. The core clock can be divided downfrom 2 to 5 in half clock increments to generate theSDRAM clock. SDRAM frequencies between 79 MHz and100 MHz are only supported for certain types of closedsystems and strict design rules must be adhered to. Forfurther details, contact your local National Semiconductortechnical support representative.A basic block diagram of the memory controller is shownin Figure 4-3.SDRAMSequenceControllerTimingControllerDQM[7:0]RASA#,RASB#CASA#,CASB#CS[3:0]#WEA#/WEB#CKEA, CKEBGeode GXLV Processor SeriesConfigurationRegistersProcessor/PCI AddressDisplay Controller AddressGraphics Pipeline AddressAddressControl/MUXMA[12:0]BA[1:0]Processor/PCI DataProcessor/PCIWrite Buffer (16 Bytes)Display Controller DataDisplay ControllerWrite Buffer (16 Bytes)MD[63:0]Graphics Pipeline DataGraphics ControllerWrite Buffer (16 Bytes)Read Buffer(16 Bytes)Core Clock (ph2)Clock Divider2, 2.5, 3, 3.5, 4, 4.5, 5SDCLK[3:0]Figure 4-3. Memory Controller Block DiagramRevision 1.3 107 www.national.com
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Geode GXLV Processor Series Low Pow
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