Geode GXLV Processor Series Low Power Integrated x86 Solutions

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Geode GXLV Processor SeriesIntegrated Functions (Continued)A VGA is made up of several functional units.• The frame buffer is 256 KB of memory that providesdata for the video display. It is organized as 64 K 32-bitDWORDs.• The sequencer decomposes word and DWORD CPUaccesses into byte operations for the graphicscontroller. It also controls a number of miscellaneousfunctions, including reset and some clocking controls.• Thegraphics controller provides most of the interfacebetween CPU data and the frame buffer. It allows theprogrammer to read and write frame buffer data indifferent formats. Plus provides ROP (raster operation)and masking functions.• The CRT controller provides video timing signals andaddress generation for video refresh. It also provides atext cursor.• The attribute controller contains the video refreshdatapath, including text rasterization and palettelookup.• The general registers provide status information forthe programmer as well as control over VGA-hostaddress mapping and clock selection. This is allhandled in hardware by the graphics pipeline.It is important to understand that a VGA is constructed ofnumerous independent functions. Most of the registerfields correspond to controls that were originally built outof discrete logic or were part of a dedicated controllersuch as the 6845. The notion of a VGA “mode” is a higherlevelconvention to denote a particular set of values for theregisters. Many popular programs do not use standardmodes, preferring instead to produce their own VGA setupsthat are optimal for their purposes.4.6.1.1 VGA Memory OrganizationThe VGA memory is organized as 64K 32-bit DWORDs.This organization is usually presented as four 64 KB“planes”. A plane consists of one byte out of everyDWORD. Thus, plane 0 refers to the least significant bytefrom every one of the 64K DWORDs. The addressinggranularity of this memory is a DWORD, not a byte; that is,consecutive addresses refer to consecutive DWORDs.The only provision for byte-granularity addressing is thefour-byte enable signals used for writes. In C parlance,single_plane_byte = (dword_fb[address] >>(plane * 8)) & 0xFF;When dealing with VGA, it is important to recognize thedistinction between host addresses, frame bufferaddresses, and the refresh address pipe. A VGA controllercontains a lot of hardware to translate between theseaddress spaces in different ways, and understandingthese translations is critical to understanding the entiredevice. In standard four-plane graphics modes, a framebufferDWORD provides eight 4-bit pixels. The left-mostpixel comes from bit 7 of each plane, with plane 3 providingthe most significant bit.pixel[i].bit[j] = dword_fb[address].bit[i*8 + (7-j)]4.6.1.2 VGA Front EndThe VGA front end consists of address and data translationsbetween the CPU and the frame buffer. This functionalityis contained within the graphics controller andsequencer components. Most of the front end functionalityis implemented in the VGA read and write hardware of theGXLV processor. An important axiom of the VGA is thatthe front end and back end are controlled independently.There are no register fields that control the behavior ofboth pieces. Terms like “VGA odd/even mode” are thereforesomewhat misleading; there are two different controlsfor odd/even functionality in the front end, and two separatecontrols in the refresh path to cause “sensible”refresh behavior for frame buffer contents written inodd/even mode. Normally, all these fields would be set uptogether, but they don’t have to be. This sort of orthogonalbehavior gives rise to the enormous number of possibleVGA “modes”. The CPU end of the read and write pipelinesis one byte wide. Word and DWORD accesses fromthe CPU to VGA memory are broken down into multiplebyte accesses by the sequencer. For example, a wordwrite to A0000h (in a VGA graphics mode) is processedas if it were two-byte write operations to A0000h andA0001h.4.6.1.3 Address MappingWhen a VGA card sees an address on the host bus, bits[31:15] determine whether the transaction is for the VGA.Depending on the mode, addresses 000AXXXX,000B{0xxx}XXX, or 000B{1xxx}XXX can decode into VGAspace. If the access is for the VGA, bits [15:0] provide theDWORD address into the frame buffer (see odd/even andChain 4 modes, next paragraph). Thus, each byte addresson the host bus addresses a DWORD in VGA memory.On a write transaction, the byte enables are normallydriven from the sequencer’s MapMask register. The VGAhas two other write address mappings that modify thisbehavior. In odd/even (Chain 2) write mode, bit 0 of theaddress is used to enable bytes 0 and 2 (if zero) or bytes1 and 3 (if one). In addition, the address presented to theframe buffer has bit 0 replaced with the PageBit field ofthe Miscellaneous Output register. Chain 4 write mode issimilar; only one of the four byte enables is asserted,based on bits [1:0] of the address, and bits [1:0] of theframe buffer address are set to zero. In each of thesemodes, the MapMask enables are logically ANDed intothe enables that result from the address.www.national.com 158 Revision 1.3
Integrated Functions (Continued)4.6.1.4 Video RefreshVGA refresh is controlled by two units: the CRT controller(CRTC) and the attribute controller (ATTR). The CRTCprovides refresh addresses and video control; the ATTRprovides the refresh datapath, including pixel formattingand internal palette lookup.The VGA back end contains two basic clocks: the dotclock (or pixel clock) and the character clock. The Clock-Select field of the Miscellaneous Output register selects a“master clock” of either 25 MHz or 28 MHz. This masterclock, optionally divided by two, drives the dot clock. Thecharacter clock is simply the dot clock divided by eight ornine.The VGA supports four basic pixel formats. Using text format,the VGA interprets frame buffer values as ASCIIcharacters, foreground/background attributes, and fontdata. The other three formats are all “graphics modes”,known as APA (All Points Addressable) modes. These formatscould be called CGA-compatible (odd/even 4-bpp),EGA-compatible (4-plane 4-bpp), and VGA-compatible(pixel-per-byte 8-bpp). The format is chosen by theShiftRegister field of the Graphics Controller Mode register.The refresh address pipe is an integral part of the CRTC,and has many configuration options. Refresh can begin atany frame buffer address. The display width and the framebuffer pitch (scan-line delta) are set separately. Multiplescan lines can be refreshed from the same frame bufferaddresses. The LineCompare register causes the refreshaddress to be reset to zero at a particular scan line, providingsupport for vertical split-screen.Within the context of a single scan line, the refreshaddress increments by one on every character clock.Before being presented to the frame buffer, refreshaddresses can be shifted by 0, 1, or 2 bits to the left.These options are often mis-named BYTE, WORD, andDWORD modes. Using this shifter, the refresh unit can beprogrammed to skip one out of two or three out of fourDWORDs of refresh data. As an example of the utility ofthis function, consider Chain 4 mode, described in Section4.6.1.3 “Address Mapping” on page 158. Pixels written inChain 4 mode occupy one out of every four DWORDs inthe frame buffer. If the refresh path is put into “Doubleword”mode, the refresh will come only from thoseDWORDs writable in Chain 4. This is how VGA mode 13hworks.In text mode, the ATTR has a lot of work to do. At eachcharacter clock, it pulls a DWORD of data out of the framebuffer.InthatDWORD,plane0containstheASCIIcharactercode, and plane 1 contains an attribute byte. TheATTR uses plane 0 to generate a font lookup address andread another DWORD. In plane 2, this DWORD contains abit-per-pixel representation of one scan line in the appropriatecharacter glyph. The ATTR transforms these bitsinto eight pixels, obtaining foreground and backgroundcolors from the attribute byte. The CRTC must refreshfrom the same memory addresses for all scan lines thatmake up a character row; within that row, the ATTR mustfetchsuccessivescanlinesfromtheglyphtablesoastodraw proper characters. Graphics modes are somewhatsimpler. In CGA-compatible mode, a DWORD provideseight pixels. The first four pixels come from planes 0 and2; each 4-bit pixel gets bits [3:2] from plane 2, and bits[1:0] from plane 0. The remaining four pixels come fromplanes 1 and 3. The EGA-compatible mode also getseight pixels from a DWORD, but each pixel gets one bitfrom each plane, with plane 3 providing bit 3. Finally,VGA-compatible mode gets four pixels from eachDWORD; plane 0 provides the first pixel, plane 1 the next,and so on. The 8 bpp mode uses an option to provideevery pixel for two dot clocks, thus allowing the refreshpipe to keep up (it only increments on character clocks)and meaning that the 320-pixel-wide mode 13h really has640 visible pixels per line. The VGA color model isunusual. The ATTR contains a 16-entry color palette with6 bits per entry. Except for 8 bpp modes, all VGA configurationsdrive four bits of pixel data into the palette, whichproduces a 6-bit result. Based on various control registers,this value is then combined with other register contentsto produce an 8-bit index into the DAC. There is aColorPlaneEnable register to mask bits out of the pixeldata before it goes to the palette; this is used to emulatefour-color CGA modes by ignoring the top two bits of eachpixel. In 8 bpp modes, the palette is bypassed and thepixel data goes directly to the DAC.4.6.1.5 VGA Video BIOSThe video BIOS supports the VESA BIOS Extensions(VBE) Version 1.2 and 2.0, as well as all standard VGABIOS calls. It interacts with Virtual VGA through the use ofseveral extended VGA registers. These are virtual registerscontained in the VSA code for Virtual VGA. (Theseregisters are defined in a separate document.)4.6.2 Virtual VGAThe GXLV processor reduces the burden of legacy hardwareby using a balanced mix of hardware and software toprovide the same functionality. The graphics pipeline containsfull hardware support for the VGA “front-end”, thelogic that controls read and write operations to the VGAframe buffer (located in graphics memory). For somemodes, the hardware can also provide direct display of thedata in the VGA buffer. Virtual VGA traps frame bufferaccesses only when necessary, but it must trap all VGAI/O accesses to maintain the VGA state and properly programthe graphics pipeline and display controller.The processor core contains SMI generation hardware forVGA memory write operations. The bus controller containsSMI generation hardware for VGA I/O read and writeoperations. The graphics pipeline contains hardware todetect and process reads and writes to VGA memory.VGA memory is partitioned from system memory.VGA functionality with the GXLV processor includes thestandard VGA modes (VGA, EGA, CGA, and MDA) aswell as the higher-resolution VESA modes. The CGA andMDA modes (modes 0 through 7) require that Virtual VGAGeode GXLV Processor SeriesRevision 1.3 159 www.national.com
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