Geode GXLV Processor Series Low Power Integrated x86 Solutions

More documents

Recommendations

Info

Geode GXLV Processor SeriesIntegrated Functions (Continued)Bit Name DescriptionTable 4-15. Memory Controller Registers (Continued)7 RSVD Reserved: Set to 0.6:4 DPL Data-in to PRE command period (tDPL): Minimum number of SDRAM clocks from the time the lastwrite datum is sampled till the bank is precharged:000 = Reserved 010 = 2 CLK 100 = 4 CLK 110 = 6 CLK001 = 1 CLK 011 = 3 CLK 101 = 5 CLK 111 = 7 CLK3:0 RSVD Reserved: Leave unchanged. Always returns a 101h.Note: Refer to SDRAM device specifications available from SDRAM manufacturer’s for more detailed informationGX_BASE+8414h-8417h MC_GBASE_ADD (R/W) Default Value = 00000000h31:18 RSVD Reserved: Set to 0.17 TE Test Enable TEST[3:0]:0 = TEST[3:0] are driven low (normal operation)1 = TEST[3:0] pins are used to output test information16 TECTL Test Enable Shared Control Pins:0 = RASB#, CASB#, CKEB, WEB# (normal operation)1 = RASB#, CASB#, CKEB, WEB# are used to output test information15:12 SEL Select: This field is used for debug purposes only. Should be left at zero for normal operation.11 RSVD Reserved: Set to 0.10:0 GBADD Graphics Base Address: This field indicates the graphics memory base address, which is programmableon 512 KB boundaries. This field corresponds to address bits [29:19].Note that BC_DRAM_TOP must be set to a value lower than the Graphics Base Address.GX_BASE+8418h-841Bh MC_DR_ADD (R/W) Default Value = 00000000h31:10 RSVD Reserved: Set to 0.9:0 DRADD Dirty RAM Address: This field is the address index that is used to access the Dirty RAM with theMC_DR_ACC register. This field does not auto increment.GX_BASE+841Ch-841Fh MC_DR_ACC (R/W) Default Value = 0000000xh31:2 RSVD Reserved: Set to 0.1 D Dirty Bit: This bit is read/write accessible.0 V Valid Bit: This bit is read/write accessible.www.national.com 116 Revision 1.3
Integrated Functions (Continued)4.3.5 Address TranslationThe memory controller supports two address translationsdepending on the method used to interleave pages. Thehardware automatically enables high order interleaving.Low order interleaving is automatically enabled only underspecific memory configurations.4.3.5.1 High Order InterleavingHigh Order Interleaving (HOI) uses the most significantaddress bits to select which bank the page is located in.This interleaving scheme works with any mixture of DIMMtypes. However, it spreads the pages over wide addressranges. For example, two 8 MB DIMMs contain a total offour component pages. Two pages are together in oneDIMM separated from the other two pages by 8 MB.4.3.5.2 Auto Low Order InterleavingThe memory controller requires that banks 0:1 if bothinstalled, be identical and banks 2:1 if both installed, beidentical. When banks 0:1 are installed or banks 2,3 areinstalled Auto Low Order Interleaving (LOI) is in effect forthose bank pairs. Therefore each DIMM (banks 0:1 or 2:3)must have the same number of DIMM banks, componentbanks, module sizes and page sizes.LOI uses the least significant bits after the page bits toselect which bank the page is located in. This requiresthat memory is a power of 2, that the number of banks is apower of 2, and that the page sizes are the same. Asstated before, for LOI to work, the DIMMs have to be ofthe same type. LOI does give a good benefit by providinga moving page throughout memory. Using the sameexample as above, two banks would be on one DIMM andthe next two banks would be on the second DIMM, butthey would be linear in address space. For an eight banksystem that has 1 KB address (8 KB data) pages, therewould be an effective moving page of 64 KB of data.4.3.5.3 Physical Address to DRAM AddressConversionTables 4-16 and 4-17 give Auto LOI address conversionexamples when two DIMMs of the same size are used in asystem. Table 4-16 shows a one DIMM bank conversionexample, while Table 4-17 shows a two DIMM bank example.Tables 4-18 and 4-19 give Non-Auto LOI address conversionexamples when either one or two DIMMs of differentsizesareusedinasystem.Table4-18showsaoneDIMMbank address conversion example, while Table 4-19shows a two DIMM bank example. The addresses arecomputed on a per DIMM basis.Since the DRAM interface is 64 bits wide, the lower threebits of the physical address get mapped onto theDQM[7:0] lines. Thus, the address conversion tables(Tables 4-16 through 4-19) show the physical addressstarting from A3.Geode GXLV Processor SeriesRevision 1.3 117 www.national.com
Page 4 and 5:
Geode GXLV Processor SeriesTable of
Page 6 and 7:
Page 8:
Page 12 and 13:
Geode GXLV Processor SeriesArchitec
Page 15 and 16:
Architecture Overview (Continued)Ge
Page 17 and 18:
Architecture Overview (Continued)SD
Page 19 and 20:
2.0 Signal DefinitionsThis section
Page 21 and 22:
Signal Definitions (Continued)Index
Page 23 and 24:
Signal Definitions (Continued)PinNo
Page 25 and 26:
Signal Definitions (Continued)Table
Page 27 and 28:
Signal Definitions (Continued)PinNo
Page 29 and 30:
Signal Definitions (Continued)Table
Page 31 and 32:
Signal Definitions (Continued)2.2 S
Page 33 and 34:
Signal Definitions (Continued)2.2.2
Page 35 and 36:
Page 37 and 38:
Page 39 and 40:
Page 41 and 42:
3.0 Processor ProgrammingThis secti
Page 43 and 44:
Processor Programming (Continued)3.
Page 45 and 46:
Page 47 and 48:
Page 49 and 50:
Processor Programming (Continued)Bi
Page 51 and 52:
Processor Programming (Continued)Ta
Page 53 and 54:
Processor Programming (Continued)Bi
Page 55 and 56:
Page 57 and 58:
Page 59 and 60:
Page 61 and 62:
Processor Programming (Continued)Th
Page 63 and 64:
Page 65 and 66: Processor Programming (Continued)Ad
Page 67 and 68: Processor Programming (Continued)3.
Page 69 and 70: Processor Programming (Continued)Se
Page 73 and 74: Processor Programming (Continued)TY
Page 75 and 76: Processor Programming (Continued)Ta
Page 89 and 90: Processor Programming (Continued)Wh
Page 95 and 96: Processor Programming (Continued)Bi
Page 97 and 98: Integrated Functions (Continued)4.1
Page 101 and 102: Integrated Functions (Continued)Mne
Page 105 and 106: Integrated Functions (Continued)Bit
Page 111 and 112: Integrated Functions (Continued)ACT
Page 115: Integrated Functions (Continued)Bit
Page 119 and 120: Integrated Functions (Continued)Tab
Page 121 and 122: Integrated Functions (Continued)SDR
Page 137 and 138: Integrated Functions (Continued).Re
Page 139 and 140: Integrated Functions (Continued)640
Page 143 and 144: Integrated Functions (Continued)GX_
Page 145 and 146: Integrated Functions (Continued)11:
Page 149 and 150: Integrated Functions (Continued)9:0
Page 167 and 168:
Integrated Functions (Continued)4.7
Page 169 and 170:
Integrated Functions (Continued)Bit
Page 171 and 172:
Integrated Functions (Continued)Bit
Page 173 and 174:
Page 175 and 176:
Page 177 and 178:
Power Management (Continued)CPU Sus
Page 179 and 180:
Power Management (Continued)5.2.2 I
Page 181 and 182:
Power Management (Continued)5.3 POW
Page 183 and 184:
Power Management (Continued)Table 5
Page 185 and 186:
Electrical Specifications (Continue
Page 187 and 188:
Page 189 and 190:
Page 191 and 192:
Page 193 and 194:
Page 195 and 196:
Page 197 and 198:
Page 199 and 200:
Page 201 and 202:
Page 203 and 204:
Page 205 and 206:
Page 207 and 208:
7.0 Instruction SetThis section sum
Page 209 and 210:
Instruction Set (Continued)7.1.2.3
Page 211 and 212:
Page 213 and 214:
Page 215 and 216:
Page 217 and 218:
Instruction Set (Continued)Table 7-
Page 219 and 220:
Instruction Set (Continued)Instruct
Page 221 and 222:
Instruction Set (Continued)JMP Unco
Page 223 and 224:
Page 225 and 226:
Page 227 and 228:
Page 229 and 230:
Page 231 and 232:
Page 233 and 234:
Instruction Set (Continued)7.5 MMX
Page 235 and 236:
Instruction Set (Continued)PCMPEQB
Page 237 and 238:
Instruction Set (Continued)PUNPCKHW
Page 239 and 240:
Page 241 and 242:
Package Specifications (Continued)C
Page 243 and 244:
Package Specifications (Continued)8
Page 245 and 246:
Package Specifications (Continued)S
Page 247:
Geode GXLV Processor Series Low Pow
show all

Geode GXLV Processor Series Low Power Integrated x86 Solutions

Create successful ePaper yourself

Delete template?

Save as template?