Geode GXLV Processor Series Low Power Integrated x86 Solutions

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Geode GXLV Processor SeriesInstruction Set (Continued)INC Increment by 1Register/Memory F [111w] [mod 000 r/m] x - - - x x x x - 1 1 b hRegister (short form) 4 [0 reg] 1 1INT Software InterruptINT i CD # - - x 0 - - - - - 19 b,e g,j,k,rProtected Mode:-Interrupt or Trap to Same Privilege-Interrupt or Trap to Different Privilege-16-bit Task to 16-bit TSS by Task Gate-16-bit Task to 32-bit TSS by Task Gate-16-bit Task to V86 by Task Gate-16-bit Task to 16-bit TSS by Task Gate-32-bit Task to 32-bit TSS by Task Gate-32-bit Task to V86 by Task Gate-V86 to 16-bit TSS by Task Gate-V86 to 32-bit TSS by Task Gate-V86 to Privilege 0 by Trap Gate/Int GateINT 3 CC INT INTINTOIf OF==0If OF==1 (INT 4)InstructionTable 7-27. Processor Core Instruction Set Summary (Continued)CEINVD Invalidate Cache 0F 08 - - - - - - - - - 20 20 t tINVLPG Invalidate TLB Entry 0F 01 [mod 111 r/m] - - - - - - - - - 15 15IRET Interrupt ReturnReal Mode CF x x x x x x x x x 13 g,h,j,k,rProtected Mode:-Within Task to Same Privilege-Within Task to Different Privilege-16-bit Task to 16-bit Task-16-bit Task to 32-bit TSS-16-bit Task to V86 Task-32-bit Task to 16-bit TSS-32-bit Task to 32-bit TSS-32-bit Task to V86 TaskJB/JNAE/JC Jump on Below/Not Above or Equal/CarryOpcode8-bit Displacement 72 + - - - - - - - - - 1 1 rFull Displacement 0F 82 +++ 1 1JBE/JNA Jump on Below or Equal/Not Above8-bit Displacement 76 + - - - - - - - - 1 1 rFull Displacement 0F 86 +++ 1 1JCXZ/JECXZ Jump on CX/ECX Zero E3 + - - - - - - - - - 2 2 rJE/JZ Jump on Equal/Zero8-bit Displacement 74 + - - - - - - - - 1 1 rFull Displacement 0F 84 +++ 1 1JL/JNGE Jump on Less/Not Greater or Equal8-bit Displacement 7C + - - - - - - - - 1 1 rFull Displacement 0F 8C +++ 1 1JLE/JNG Jump on Less or Equal/Not Greater8-bit Displacement 7E + - - - - - - - - 1 1 rFull Displacement 0F 8E +++ 1 1FlagsO D I T S Z A P CF F F F F F F F FRealMode4INTProt’dModeClock Count(Reg/Cache Hit)3355184190124187193127187193644INT2039169175109172178112RealModeProt’dModeIssueswww.national.com 220 Revision 1.3
Instruction Set (Continued)JMP Unconditional JumpInstruction8-bit Displacement EB + - - - - - - - - 1 1 b h,j,k,rFull Displacement E9 +++ 1 1Register/Memory Indirect Within Segment FF [mod 100 r/m] 1/3 1/3Direct Intersegment-Call Gate Same Privilege Level-16-bit Task to 16-bit TSS-16-bit Task to 32-bit TSS-16-bit Task to V86 Task-32-bit Task to 16-bit TSS-32-bit Task to 32-bit TSS-32-bit Task to V86 TaskIndirect Intersegment-Call Gate Same Privilege Level-16-bit Task to 16-bit TSS-16-bit Task to 32-bit TSS-16-bit Task to V86 Task-32-bit Task to 16-bit TSS-32-bit Task to 32-bit TSS-32-bit Task to V86 TaskTable 7-27. Processor Core Instruction Set Summary (Continued)EAOpcode[unsigned full offset,selector]8 1222186192126189195129FF [mod 101 r/m] 10 1323187193127190196130JNB/JAE/JNC Jump on Not Below/Above or Equal/Not Carry8-bit Displacement 73 + - - - - - - - - 1 1 rFull Displacement 0F 83 +++ 1 1JNBE/JA Jump on Not Below or Equal/Above8-bit Displacement 77 + - - - - - - - - 1 1 rFull Displacement 0F 87 +++ 1 1JNE/JNZ Jump on Not Equal/Not Zero8-bit Displacement 75 + - - - - - - - - 1 1 rFull Displacement 0F 85 +++ 1 1JNL/JGE Jump on Not Less/Greater or Equal8-bit Displacement 7D + - - - - - - - - 1 1 rFull Displacement 0F 8D +++ 1 1JNLE/JG Jump on Not Less or Equal/Greater8-bit Displacement 7F + - - - - - - - - 1 1 rFull Displacement 0F 8F +++ 1 1JNO Jump on Not Overflow8-bit Displacement 71 + - - - - - - - - 1 1 rFull Displacement 0F 81 +++ 1 1JNP/JPO Jump on Not Parity/Parity Odd8-bit Displacement 7B + - - - - - - - - 1 1 rFull Displacement 0F 8B +++ 1 1JNS Jump on Not Sign8-bit Displacement 79 + - - - - - - - - 1 1 rFull Displacement 0F 89 +++ 1 1JO Jump on Overflow8-bit Displacement 70 + - - - - - - - - 1 1 rFull Displacement 0F 80 +++ 1 1JP/JPE Jump on Parity/Parity Even8-bit Displacement 7A + - - - - - - - - 1 1 rFull Displacement 0F 8A +++ 1 1JS Jump on Sign8-bit Displacement 78 + - - - - - - - - 1 1 rFull Displacement 0F 88 +++ 1 1LAHF Load AH with Flags 9F - - - - - - - - - 2 2LAR Load Access RightsFrom Register/Memory 0F 02 [mod reg r/m] - - - - - x - - - 9 a g,h,j,pLDS Load Pointer to DS C5 [mod reg r/m] - - - - - - - - - 4 9 b h,i,jFlagsO D I T S Z A P CF F F F F F F F FRealModeProt’dModeClock Count(Reg/Cache Hit)RealModeProt’dModeIssuesGeode GXLV Processor SeriesRevision 1.3 221 www.national.com
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Geode GXLV Processor SeriesTable of
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Geode GXLV Processor SeriesArchitec
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Architecture Overview (Continued)Ge
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Architecture Overview (Continued)SD
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2.0 Signal DefinitionsThis section
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Signal Definitions (Continued)Index
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Signal Definitions (Continued)PinNo
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Signal Definitions (Continued)Table
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Signal Definitions (Continued)PinNo
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Signal Definitions (Continued)Table
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Signal Definitions (Continued)2.2 S
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Signal Definitions (Continued)2.2.2
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3.0 Processor ProgrammingThis secti
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Integrated Functions (Continued)4.1
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Geode GXLV Processor Series Low Power Integrated x86 Solutions

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