Geode GXLV Processor Series Low Power Integrated x86 Solutions

Integrated Functions (Continued)4.7.8 PCI CyclesThe following sections and diagrams provide the functionalrelationships for PCI cycles.4.7.8.1 PCI Read TransactionA PCI read transaction consists of an address phase andone or more data phases. Data phases may consist ofwait cycles and a data transfer. Figure 4-18 illustrates aPCI read transaction. In this example, there are three dataphases.The address phase begins on clock 2 when FRAME# isasserted. During the address phase, AD[31:0] contains avalid address and C/BE[3:0]# contains a valid bus command.The first data phase begins on clock 3. During thedata phase, AD[31:0] contains data and C/BE[3:0]# indicatewhich byte lanes of AD[31:0] carry valid data. Thefirst data phase completes with zero delay cycles. However,the second phase is delayed one cycle because thetarget was not ready so it deasserted TRDY# on clock 5.The last data phase is delayed one cycle because themaster deasserted IRDY# on clock 7.For additional information refer to Chapter 3.3.1, ReadTransaction, of the PCI Local Bus Specification, Revision2.1.Geode GXLV Processor SeriesCLKFRAME#ADADDRDATA-1 DATA-2 DATA-3C/BE#IRDY#BUS CMDWAITBE#sDATA TRANSFERWAITDATA TRANSFERWAITDATA TRANSFERTRDY#DEVSEL#ADDRPHASEDATAPHASEDATAPHASEDATAPHASEBUS TRANSACTIONFigure 4-18. Basic Read OperationRevision 1.3 173 www.national.com