Geode GXLV Processor Series Low Power Integrated x86 Solutions

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Geode GXLV Processor SeriesProcessor Programming (Continued)Table 3-35. SMM Memory Space Header DescriptionName Description SizeDR7 Debug Register 7: The contents of Debug Register 7. 4 BytesEFLAGS Extended Flags Register: The contents of Extended Flags Register. 4 BytesCR0 Control Register 0: The contents of Control Register 0. 4 BytesCurrent IPCurrent Instruction Pointer: The address of the instruction executed prior to servicing SMM 4Bytesinterrupt.Next IPNext Instruction Pointer: The address of the next instruction that will be executed after exiting 4BytesSMM.CS Selector Code Segment Selector: Code segment register selector for the current code segment. 2 BytesCS Descriptor Code Segment Descriptor: Encoded descriptor bits for the current code segment. 8 BytesN Nested SMI Status: Flag that determines whether an SMI occurred during SMM (i.e., nested). 1 BitV SoftVGA SMI Status: SMI was generated by an access to VGA region. 1 BitXExternal SMI Status:If = 1: SMI generated by external SMI# pin.If = 0: SMI internally generated by Internal Bus Interface Unit.1BitM Memory or I/O Access: 0 = I/O access; 1 = Memory access. 1 BitHHalt Status: Indicates that the processor was in a halt or shutdown prior to servicing the SMM 1Bitinterrupt.SSoftware SMM Entry Indicator:If = 1: Current SMM is the result of an SMINT instruction.If = 0: Current SMM is not the result of an SMINT instruction.1BitPICI/O Data SizeREP INSx/OUTSx Indicator:If = 1: Current instruction has a REP prefix.If = 0: Current instruction does not have a REP prefix.IN, INSx, OUT, or OUTSx Indicator:If = 1: Current instruction performed is an I/O WRITE.If = 0: Current instruction performed is an I/O READ.CS Writable: Code Segment WritableIf = 1: CS is writableIf = 0: CS is not writableIndicates size of data for the trapped I/O cycle:01h = BYTE03h = WORD0Fh = DWORD1Bit1Bit1Bit2BytesI/O Address Processor port used for the trapped I/O cycle 2BytesI/O or Memory Data Data associated with the trapped I/O or memory cycle 4BytesRestored ESI or EDI Restored ESI or EDI Value: Used when it is necessary to repeat a REP OUTSx or REP INSx 4Bytesinstruction when one of the I/O cycles caused an SMI# trap.Memory Address Physical address of the operation that caused the SMI 4BytesNote: INSx = INS, INSB, INSW or INSD instruction.OUTSx = OUTS, OUTSB, OUTSW and OUTSD instruction.www.national.com 86 Revision 1.3
Processor Programming (Continued)3.7.5 SMM InstructionsThe GXLV processor core automatically saves a minimalamount of CPU state information when entering SMMwhich allows fast SMM service routine entry and exit.After entering the SMM service routine, the MOV, SVDC,SVLDT and SVTS instructions can be used to save thecomplete CPU state information. If the SMM service routinemodifies more state information than is automaticallysaved or if it forces the CPU to power down, the completeCPU state information must be saved. Since the CPU is astatic device, its internal state is retained when the inputclock is stopped. Therefore, an entire CPU-state save isnot necessary before stopping the input clock.The SMM instructions, listed in Table 3-36, can be executedonly if all the conditions listed below are met.1. USE_SMI = 1.2. SMAR size > 0.3. Current Privilege Level = 0.4. SMACbitishighortheCPUisinanSMMserviceroutine.If any one of the conditions above is not met and anattempt is made to execute an SVDC, RSDC, SVLDT,RSLDT, SVTS, RSTS, or RSM instruction, an invalidopcode exception is generated. The SMM instructions canbe executed outside of defined SMM space provided theconditions above are met.The SMINT instruction can be used by software to enterSMM. The SMINT instruction can only be used outside anSMM routine if all the conditions listed below are true.1. USE_SMI = 12. SMAR size > 03. Current Privilege Level = 04. SMAC = 1If SMI# is asserted to the CPU during a software SMI, thehardware SMI# is serviced after the software SMI hasbeen exited by execution of the RSM instruction.All the SMM instructions (except RSM and SMINT) saveor restore 80 bits of data, allowing the saved values toinclude the hidden portion of the register contents.Geode GXLV Processor SeriesTable 3-36. SMM Instruction SetInstruction Opcode Format DescriptionSVDC 0F 78h [mod sreg3 r/m] SVDC mem80, sreg3 Save Segment Register and Descriptor:Saves reg (DS, ES, FS, GS, or SS) to mem80.RSDC 0F 79h [mod sreg3 r/m] RSDC sreg3, mem80 Restore Segment Register and Descriptor:Restores reg (DS, ES, FS, GS, or SS) from mem80. Use RSMto restore CS.Note: Processing “RSDC CS, mem80” will produce an exception.SVLDT 0F 7Ah [mod 000 r/m] SVLDT mem80 Save LDTR and Descriptor:Saves Local Descriptor Table (LDTR) to mem80.RSLDT 0F 7Bh [mod 000 r/m] RSLDT mem80 Restore LDTR and Descriptor:Restores Local Descriptor Table (LDTR) from mem80.SVTS 0F 7Ch [mod 000 r/m] SVTS mem80 Save TSR and Descriptor:Saves Task State Register (TSR) to mem80.RSTS 0F 7Dh [mod 000 r/m] RSTS mem80 Restore TSR and Descriptor:Restores Task State Register (TSR) from mem80.SMINT 0F 38h SMINT Software SMM Entry:CPU enters SMM. CPU state information is saved in SMMmemory space header and execution begins at SMM baseaddress.RSM 0F AAh RSM Resume Normal Mode:Exits SMM. The CPU state is restored using the SMM memoryspace header and execution resumes at interrupted point.Note: mem80 = 80-bit memory location.Revision 1.3 87 www.national.com
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Architecture Overview (Continued)Ge
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2.0 Signal DefinitionsThis section
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Signal Definitions (Continued)PinNo
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Signal Definitions (Continued)Table
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Signal Definitions (Continued)PinNo
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Power Management (Continued)Table 5
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Electrical Specifications (Continue
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Geode GXLV Processor Series Low Pow
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