Geode GXLV Processor Series Low Power Integrated x86 Solutions

Integrated Functions (Continued)4.3 MEMORY CONTROLLERThe memory controller arbitrates requests from the X-Bus(processor and PCI), display controller, and graphics pipeline.The GXLV processor supports LVTTL (low voltage TTL)technology. LVTTL technology allows the SDRAM interfaceof the memory controller to run at frequencies up to100 MHz.The SDRAM clock is a function of the core clock. TheSDRAM bus can be run at speeds that range between 66Processor/PCIControlDisplay ControllerControlGraphics PipelineControlProcessor/PCI I/FDisplay Controller I/FGraphics Pipeline I/FRFSHArbiterMHz and 100 MHz. The core clock can be divided downfrom 2 to 5 in half clock increments to generate theSDRAM clock. SDRAM frequencies between 79 MHz and100 MHz are only supported for certain types of closedsystems and strict design rules must be adhered to. Forfurther details, contact your local National Semiconductortechnical support representative.A basic block diagram of the memory controller is shownin Figure 4-3.SDRAMSequenceControllerTimingControllerDQM[7:0]RASA#,RASB#CASA#,CASB#CS[3:0]#WEA#/WEB#CKEA, CKEBGeode GXLV Processor SeriesConfigurationRegistersProcessor/PCI AddressDisplay Controller AddressGraphics Pipeline AddressAddressControl/MUXMA[12:0]BA[1:0]Processor/PCI DataProcessor/PCIWrite Buffer (16 Bytes)Display Controller DataDisplay ControllerWrite Buffer (16 Bytes)MD[63:0]Graphics Pipeline DataGraphics ControllerWrite Buffer (16 Bytes)Read Buffer(16 Bytes)Core Clock (ph2)Clock Divider2, 2.5, 3, 3.5, 4, 4.5, 5SDCLK[3:0]Figure 4-3. Memory Controller Block DiagramRevision 1.3 107 www.national.com