Geode GXLV Processor Series Low Power Integrated x86 Solutions

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Geode GXLV Processor SeriesProcessor Programming (Continued)3.5.3 Descriptors3.5.3.1 Global and Local Descriptor Table RegistersThe GDT and LDT descriptor tables are defined by theGlobal Descriptor Table Register (GDTR) and the LocalDescriptor Table Register (LDTR) respectively. Some textsrefer to these registers as GDT and LDT descriptors.The following instructions are used in conjunction with theGDT and LDT registers:• LGDT - Load memory to GDTR• LLDT - Load memory to LDTR• SGDT - Store GDTR to memory• SLDT - Store LDTR to memoryThe GDTR is set up in real mode using the LGDT instruction.This is possible as the LGDT instruction is one of twoinstructions that directly load a linear address (instead ofa segment relative address) in protected mode. (The otherinstruction is the Load Interrupt Descriptor Table [LIDT]).As shown in Table 3-20, the GDTR contains a BASE fieldand a LIMIT field that define the GDTs. The InterruptDescriptor Table Register (IDTR) is described in Section3.5.3.3 “Task, Gate, Interrupt, and Application and SystemDescriptors” on page 71.Also shown in Table 3-20, the LDTR is only two bytes wideas it contains only a SELECTOR field. The contents of theSELECTOR field point to a descriptor in the GDT.3.5.3.2 Segment DescriptorsThere are several types of descriptors. A segmentdescriptor defines the base address, limit, and attributesof a memory segment.The GDT or LDT can hold several types of descriptors. Inparticular, the segment descriptors are stored in either oftwo registers, the GDT or the LDT. Either of these tablescan store as many as 8,192 (2 13 ) 8-byte selectors takingas much as 64 KB of memory.The first descriptor in the GDT (location 0) is not used bythe CPU and is referred to as the “null descriptor.”Types of Segment DescriptorsThe type of memory segments are defined by correspondingtypes of segment descriptors:• Code Segment Descriptors• Data Segment Descriptors• Stack Segment Descriptors• LDT Segment DescriptorsTable 3-20.GDT, LDT and IDT Registers47 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0GDT RegisterIDT RegisterBASEBASEGlobal Descriptor Table RegisterInterrupt Descriptor Table RegisterLDT RegisterLIMITLIMITLocal Descriptor Table RegisterSELECTORwww.national.com 70 Revision 1.3
Processor Programming (Continued)3.5.3.3 Task, Gate, Interrupt, and Application andSystem DescriptorsBesides segment descriptors there are descriptors usedin task switching, switching between tasks with differentpriority and those used to control interrupt functions:• Interrupt Descriptors• Application and System Segment Descriptors• Gate Descriptors• Task State Segment DescriptorsAll descriptors have some things in common. They are alleight bytes in length and have three fields (BASE, LIMIT,and TYPE). The BASE field defines the starting locationfor the table or segment. The LIMIT field defines the sizeand the TYPE field depends on the type of descriptor.One of the main functions of the TYPE field is to definethe access rights to the associated segment or table.Interrupt DescriptorsThe Interrupt Descriptor Table is an array of 256 8-byte (4-byte for real mode) interrupt descriptors, each of which isused to point to an interrupt service routine. Every interruptthat may occur in the system must have an associatedentry in the IDT. The contents of the IDTR arecompletely visible to the programmer through the use ofthe SIDT instruction.The IDT is defined by the Interrupt Descriptor Table Register(IDTR). Some texts refer to this register as an IDTdescriptor.ThefollowinginstructionsareusedinconjunctionwiththeIDTR:• LIDT - Load memory to IDTR• SIDT-StoreIDTRtomemoryThe IDTR is set up in real mode using the LIDT instruction.This is possible as the LIDT instruction is only one oftwo instructions that directly load a linear address (insteadof a segment relative address) in protected mode (theother instructions is LGDT).As previously shown in Table 3-20 on page 70, the IDTRcontains a BASE ADDRESS field and a LIMIT field thatdefine the IDT tables.Application and System Segment DescriptorsThe bit structure and bit definitions for segment descriptorsare shown in Table 3-21 and Table 3-22 on page 72,respectively. The explanation of the TYPE field is showninTable3-23onpage73.Geode GXLV Processor SeriesTable 3-21. Application and System Segment Descriptors31 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Memory Offset +4BASE[31:24] G D 0 AVLLIMIT[19:16] P DPL S TYPE BASE[23:16]Memory Offset +0BASE[15:0]LIMIT[15:0]Revision 1.3 71 www.national.com
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Geode GXLV Processor Series Low Pow
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Geode GXLV Processor Series Low Power Integrated x86 Solutions

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