Geode GXLV Processor Series Low Power Integrated x86 Solutions

Integrated Functions (Continued)4.5.7.3 VGA Display SupportThe graphics pipeline contains full hardware support fortheVGAfrontend.TheVGAdataisstoredina256KBbuffer located in graphics memory. The main task for VirtualVGA (see Section 4.6 “Virtual VGA Subsystem” onpage 157) is converting the data in the VGA buffer to an 8-bpp frame buffer that can be displayed by the display controller.For some modes, the display controller can display theVGA data directly and the data conversion is not necessary.This includes standard VGA mode 13h and the variationsof that mode used in several games; the displaycontroller can also directly display VGA planar graphicsmodes D, E, F, 10, 11, and 12. Likewise, the hardware candirectly display all of the higher-resolution VESA modes.Since the frame buffer data is written directly to memoryinstead of travelling across an external bus, the GXLV processoroften outperforms VGA cards for these modes.The display controller, however, does not directly supporttext modes. SoftVGA must convert the characters andattributes in the VGA buffer to an 8-bpp frame bufferimage the hardware uses for display refresh.4.5.8 Display Controller RegistersThe Display Controller maps 100h memory locationsstarting at GX_BASE+8300h for the display controller registers.Refer to Section 4.1.2 “Control Registers” on page99 for instructions on accessing these registers.The Display Controller Registers are divided into six categories:• Configuration and Status Registers• Memory Organization Registers• Timing Registers• Cursor and Line Compare Registers• Color Registers• Palette and RAM Diagnostic RegistersTable 4-28 summarizes these registers and locations, andthe following subsections give detailed register/bit formats.Geode GXLV Processor SeriesTable 4-28. Display Controller Register SummaryGX_BASE+Memory Offset Type Name/FunctionDefaultValueConfiguration and Status Registers8300h-8303h R/W DC_UNLOCKDisplay Controller Unlock: This register is provided to lock the most critical memorymappeddisplay controller registers to prevent unwanted modification (write operations).Read operations are always allowed.8304h-8307h R/W DC_GENERAL_CFGDisplay Controller General Configuration: General control bits for the display controller.8308h-830Bh R/W DC_TIMING_CFGDisplay Controller Timing Configuration: Status and control bits for various displaytiming functions.830Ch-830Fh R/W DC_OUTPUT_CFGDisplay Controller Output Configuration: Status and control bits for pixel outputformatting functions.00000000h00000000hxx000000hxx000000hMemory Organization Registers8310h-8313h R/W DC_FB_ST_OFFSETDisplay Controller Frame Buffer Start Address: Specifies offset at which the frame bufferstarts.8314h-8317h R/W DC_CB_ST_OFFSETDisplay Controller Compression Buffer Start Address: Specifies offset at which the compresseddisplay buffer starts.8318h-831Bh R/W DC_CUR_ST_OFFSETDisplay Controller Cursor Buffer Start Address: Specifies offset at which the cursor memorybuffer starts.xxxxxxxxhxxxxxxxxhxxxxxxxxh831Ch-831Fh -- Reserved 00000000h8320h-8323h R/W DC_VID_ST_OFFSETxxxxxxxxhDisplay Controller Video Start Address: Specifies offset at which the video buffer starts.8324h-8327h R/W DC_LINE_DELTADisplay Controller Line Delta: Stores line delta for the graphics display buffers.xxxxxxxxhRevision 1.3 141 www.national.com