Geode GXLV Processor Series Low Power Integrated x86 Solutions

More documents

Recommendations

Info

Geode GXLV Processor SeriesInstruction Set (Continued)7.3 PROCESSOR CORE INSTRUCTION SETThe instruction set for the GXLV processor core is summarizedin Table 7-27. The table uses several symbolsand abbreviations that are described next and listed inTable 7-26.7.3.1 OpcodesOpcodes are given as hex values except when theyappear within brackets as binary values.7.3.2 Clock CountsThe clock counts listed in the instruction set summarytable are grouped by operating mode (real and protected)and whether there is a register/cache hit or a cache miss.In some cases, more than one clock count is shown in acolumn for a given instruction, or a variable is used in theclock count.7.3.3 FlagsThere are nine flags that are affected by the execution ofinstructions. The flag names have been abbreviated and variousconventions used to indicate what effect the instructionhas on the particular flag.Table 7-26. Processor Core Instruction SetTable LegendSymbol orAbbreviationDescriptionOpcode# Immediate 8-bit data.## Immediate 16-bit data.### Full immediate 32-bit data (8, 16, 32 bits).+ 8-bit signed displacement.+++ Full signed displacement (16, 32 bits).Clock Count/ Register operand/memory operand.n Number of times operation is repeated.L Level of the stack frame.| Conditional jump taken | Conditional jump nottaken. (e.g. “4|1” = 4 clocks if jump taken, 1clock if jump not taken).\ CPL ≤ IOPL \ CPL > IOPL(where CPL = Current Privilege Level, IOPL =I/O Privilege Level).FlagsOF Overflow Flag.DF Direction Flag.IF Interrupt Enable Flag.TF Trap Flag.SF Sign Flag.ZF Zero Flag.AF Auxiliary Flag.PF Parity Flag.CF Carry Flag.x Flag is modified by the instruction.- Flag is not changed by the instruction.0 Flag is reset to “0”.1 Flag is set to “1”.u Flag is undefined following execution theinstruction.www.national.com 216 Revision 1.3
Instruction Set (Continued)Table 7-27. Processor Core Instruction Set SummaryO D I T S Z A P C Clock CountInstructionOpcodeF F F F F F F F F (Reg/Cache Hit) IssuesAAA ASCIIAdjustALafterAdd 37 u - - - u u x u x 3 3AAD ASCII Adjust AX before Divide D5 0A u - - - x x u x u 7 7AAM ASCII Adjust AX after Multiply D4 0A u - - - x x u x u 19 19AAS ASCII Adjust AL after Subtract 3F u - - - u u x u x 3 3ADC Add with CarryRegister to Register 1 [00dw] [11 reg r/m] x - - - x x x x x 1 1 b hRegister to Memory 1 [000w] [mod reg r/m] 1 1Memory to Register 1 [001w] [mod reg r/m] 1 1Immediate to Register/Memory 8 [00sw] [mod 010 r/m]### 1 1Immediate to Accumulator 1 [010w] ### 1 1ADD Integer AddRegister to Register 0 [00dw] [11 reg r/m] x - - - x x x x x 1 1 b hRegister to Memory 0 [000w] [mod reg r/m] 1 1Memory to Register 0 [001w] [mod reg r/m] 1 1Immediate to Register/Memory 8 [00sw] [mod 000 r/m]### 1 1Immediate to Accumulator 0 [010w] ### 1 1AND Boolean ANDRegister to Register 2 [00dw] [11 reg r/m] 0 - - - x x u x 0 1 1 b hRegister to Memory 2 [000w] [mod reg r/m] 1 1Memory to Register 2 [001w] [mod reg r/m] 1 1Immediate to Register/Memory 8 [00sw] [mod 100 r/m]### 1 1Immediate to Accumulator 2 [010w] ### 1 1ARPL Adjust Requested Privilege LevelFrom Register/Memory 63 [mod reg r/m] - - - - - x - - - 9 a hBB0_Reset Set BLT Buffer 0 Pointer to the Base 0F 3A 2 2BB1_Reset Set BLT Buffer 1 Pointer to the Base 0F 3B 2 2BOUND Check Array BoundariesIf Out of Range (Int 5) 62 [mod reg r/m] - - - - - - - - - 8+INT 8+INT b, e g,h,j,k,rIf In Range 7 7BSF Scan Bit ForwardRegister, Register/Memory 0F BC [mod reg r/m] - - - - - x - - - 4/9+n 4/9+n b hBSR Scan Bit ReverseRegister, Register/Memory 0F BD [mod reg r/m] - - - - - x - - - 4/11+n 4/11+n b hBSWAP Byte Swap 0F C[1 reg] - - - - - - - - - 6 6BT Test BitRegister/Memory, Immediate 0F BA [mod 100 r/m]# - - - - - - - - x 1 1 b hRegister/Memory, Register 0F A3 [mod reg r/m] 1/7 1/7BTC Test Bit and ComplementRegister/Memory, Immediate 0F BA [mod 111 r/m]# - - - - - - - - x 2 2 b hRegister/Memory, Register 0F BB [mod reg r/m] 2/8 2/8BTR Test Bit and ResetRegister/Memory, Immediate 0F BA [mod 110 r/m]# - - - - - - - - x 2 2 b hRegister/Memory, Register 0F B3 [mod reg r/m 2/8 2/8BTS Test Bit and SetRegister/Memory 0F BA [mod 101 r/m] - - - - - - - - x 2 2 b hRegister (short form) 0F AB [mod reg r/m] 2/8 2/8FlagsRealModeProt’dModeRealModeProt’dModeGeode GXLV Processor SeriesRevision 1.3 217 www.national.com
Page 4 and 5:
Geode GXLV Processor SeriesTable of
Page 6 and 7:
Page 8:
Page 12 and 13:
Geode GXLV Processor SeriesArchitec
Page 15 and 16:
Architecture Overview (Continued)Ge
Page 17 and 18:
Architecture Overview (Continued)SD
Page 19 and 20:
2.0 Signal DefinitionsThis section
Page 21 and 22:
Signal Definitions (Continued)Index
Page 23 and 24:
Signal Definitions (Continued)PinNo
Page 25 and 26:
Signal Definitions (Continued)Table
Page 27 and 28:
Signal Definitions (Continued)PinNo
Page 29 and 30:
Signal Definitions (Continued)Table
Page 31 and 32:
Signal Definitions (Continued)2.2 S
Page 33 and 34:
Signal Definitions (Continued)2.2.2
Page 35 and 36:
Page 37 and 38:
Page 39 and 40:
Page 41 and 42:
3.0 Processor ProgrammingThis secti
Page 43 and 44:
Processor Programming (Continued)3.
Page 45 and 46:
Page 47 and 48:
Page 49 and 50:
Processor Programming (Continued)Bi
Page 51 and 52:
Processor Programming (Continued)Ta
Page 53 and 54:
Page 55 and 56:
Page 57 and 58:
Page 59 and 60:
Page 61 and 62:
Processor Programming (Continued)Th
Page 63 and 64:
Page 65 and 66:
Processor Programming (Continued)Ad
Page 67 and 68:
Page 69 and 70:
Processor Programming (Continued)Se
Page 71 and 72:
Page 73 and 74:
Processor Programming (Continued)TY
Page 75 and 76:
Processor Programming (Continued)Ta
Page 77 and 78:
Page 79 and 80:
Page 81 and 82:
Page 83 and 84:
Page 85 and 86:
Page 87 and 88:
Page 89 and 90:
Processor Programming (Continued)Wh
Page 91 and 92:
Page 93 and 94:
Page 95 and 96:
Page 97 and 98:
Integrated Functions (Continued)4.1
Page 99 and 100:
Page 101 and 102:
Integrated Functions (Continued)Mne
Page 103 and 104:
Page 105 and 106:
Integrated Functions (Continued)Bit
Page 107 and 108:
Page 109 and 110:
Page 111 and 112:
Integrated Functions (Continued)ACT
Page 113 and 114:
Page 115 and 116:
Page 117 and 118:
Page 119 and 120:
Integrated Functions (Continued)Tab
Page 121 and 122:
Integrated Functions (Continued)SDR
Page 123 and 124:
Page 125 and 126:
Page 127 and 128:
Page 129 and 130:
Page 131 and 132:
Page 133 and 134:
Page 135 and 136:
Page 137 and 138:
Integrated Functions (Continued).Re
Page 139 and 140:
Integrated Functions (Continued)640
Page 141 and 142:
Page 143 and 144:
Integrated Functions (Continued)GX_
Page 145 and 146:
Integrated Functions (Continued)11:
Page 147 and 148:
Page 149 and 150:
Integrated Functions (Continued)9:0
Page 151 and 152:
Page 153 and 154:
Page 155 and 156:
Page 157 and 158:
Page 159 and 160:
Page 161 and 162:
Page 163 and 164:
Page 165 and 166: Integrated Functions (Continued)Bit
Page 167 and 168: Integrated Functions (Continued)4.7
Page 177 and 178: Power Management (Continued)CPU Sus
Page 179 and 180: Power Management (Continued)5.2.2 I
Page 181 and 182: Power Management (Continued)5.3 POW
Page 183 and 184: Power Management (Continued)Table 5
Page 185 and 186: Electrical Specifications (Continue
Page 207 and 208: 7.0 Instruction SetThis section sum
Page 209 and 210: Instruction Set (Continued)7.1.2.3
Page 215: Instruction Set (Continued)7.2.2.3
Page 219 and 220: Instruction Set (Continued)Instruct
Page 221 and 222: Instruction Set (Continued)JMP Unco
Page 229 and 230: Instruction Set (Continued)Table 7-
Page 233 and 234: Instruction Set (Continued)7.5 MMX
Page 235 and 236: Instruction Set (Continued)PCMPEQB
Page 237 and 238: Instruction Set (Continued)PUNPCKHW
Page 241 and 242: Package Specifications (Continued)C
Page 243 and 244: Package Specifications (Continued)8
Page 245 and 246: Package Specifications (Continued)S
Page 247: Geode GXLV Processor Series Low Pow
show all

Geode GXLV Processor Series Low Power Integrated x86 Solutions

Create successful ePaper yourself

Delete template?

Save as template?