Geode GXLV Processor Series Low Power Integrated x86 Solutions

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Geode GXLV Processor SeriesProcessor Programming (Continued)Field(s)Numberof BitsDescriptionTable 3-13. DR7 and DR6 Bit DefinitionsThe Debug Status Register (DR6) reflects conditions thatwere in effect at the time the debug exception occurred.The contents of the DR6 register are not automaticallycleared by the processor after a debug exception occurs,and therefore should be cleared by software at the appropriatetime. Code execution breakpoints may also be generatedby placing the breakpoint instruction (INT3) at thelocation where control is to be regained. The single-stepfeature may be enabled by setting the TF flag (bit 8) in theEFLAGS register. This causes the processor to perform adebug exception after the execution of every instruction.DR7 RegisterDebug Control Register (R/W)R/Wn 2 Applies to the DRn breakpoint address register:00 = Break on instruction execution only01 = Break on data write operations only10 = Not used11 = Break on data reads or write operationsLENn 2 Applies to the DRn breakpoint address register:00 = One-byte length01 = Two-byte length10 = Not used11 = Four-byte lengthGn 1 If = 1: Breakpoint in DRn is globally enabled for all tasks and is not cleared by the processor as theresult of a task switch.Ln 1 If = 1: Breakpoint in DRn is locally enabled for the current task and is cleared by the processor as theresult of a task switch.GD 1 Global disable of debug register access. GD bit is cleared whenever a debug exception occurs.DR6 RegisterDebug Status Register (RO)Bn 1 Bn is set by the processor if the conditions described by DRn, R/Wn, and LENn occurred when thedebug exception occurred, even if the breakpoint is not enabled via the Gn or Ln bits.BT 1 BT is set by the processor before entering the debug handler if a task switch has occurred to a task withthe T bit in the TSS set.BS 1 BS is set by the processor if the debug exception was triggered by the single-step execution mode (TFflag, bit 8, in EFLAGS set).Note: n = 0, 1, 2, and 3www.national.com 56 Revision 1.3
Processor Programming (Continued)3.3.2.4 TLB Test RegistersTwo test registers are used in testing the processor’sTranslation Lookaside Buffer (TLB), TR6 and TR7. Table 3-14 is a register map for the TLB Test Registers with their bitdefinitions given in Table 3-15 on page 58. The test registersare accessed through MOV instructions that can beexecuted only at privilege level 0 (real mode is alwaysprivilege level 0).The CPU TLB is a 32-entry, four-way set associativememory. Each TLB entry consists of a 24-bit tag and 20-bit data. The 24-bit tag represents the high-order 20 bitsof the linear address, a valid bit, and three attribute bits.The 20-bit data portion represents the upper 20 bits of thephysical address that corresponds to the linear address.The TLB Test Control Register (TR6) contains a commandbit, the upper 20 bits of a linear address, a valid bitand the attribute bits used in the test operation. The contentsof TR6 are used to create the 24-bit TLB tag duringboth write and read (TLB lookup) test operations. Thecommand bit defines whether the test operation is a reador a write.The TLB Test Data Register (TR7) contains the upper 20bits of the physical address (TLB data field), three LRUbits, two replacement (REP) bits, and a control bit (PL).During TLB write operations, the physical address in TR7is written into the TLB entry selected by the contents ofTR6. During TLB lookup operations, the TLB dataselected by the contents of TR6 is loaded into TR7. Table3-15 lists the bit definitions for TR7 and TR6.Geode GXLV Processor SeriesTable 3-14. TLB Test Registers31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0TR7 RegisterTR6 RegisterTLB Test Data Register (R/W)Physical Address 0 0 TLB LRU 0 0 PLTLB Test Control Register (R/W)Linear Address V D D#UU#RR#REP 0 00 0 0 0 CRevision 1.3 57 www.national.com
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Geode GXLV Processor Series Low Pow
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