Geode GXLV Processor Series Low Power Integrated x86 Solutions

Geode GXLV Processor SeriesIntegrated Functions (Continued)4.3.6 Memory CyclesFigures 4-5 through 4-8 illustrate various memory cyclesthat the memory controller supports. The following subsectionsdescribe some of the supported cycles.SDCLKCS#RAS#SDRAM Read CycleFigure 4-5 shows a SDRAM read cycle. The figureassumes that a previous ACT command has presentedthe row address for the read operation. Note that the burstlength for the READ command is always two.CAS#WE#MACOL nDQMMDn n+1Figure 4-5. Basic Read Cycle with a CAS Latency of Twowww.national.com 120 Revision 1.3