Geode GXLV Processor Series Low Power Integrated x86 Solutions

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Geode GXLV Processor SeriesIntegrated Functions (Continued)4.5.9 Memory Organization RegistersThe GXLV processor utilizes a graphics memory aperturethat is up to 4 MB in size. The base address of the graphicsmemory aperture is stored in the DRAM controllerGraphics Base Address register (see GBADD ofMC_GBASE_ADD register, Table 4-15 on page 116 ). Thegraphics memory is made up of the normal uncompressedframe buffer, compressed display buffer, and cursorbuffer. Each buffer begins at a programmable offsetwithin the graphics memory aperture.Thevariousmemorybuffersarearrangedsoastoefficientlypack the data within the graphics memory aperture.The arrangement is programmable to efficientlyaccommodate different display modes. The cursor bufferis a linear block so addressing is straightforward. Theframe buffer and compressed display buffer are arrangedbased upon scan lines. Each scan line has a maximumnumber of valid or active DWORDs, and a delta, whichwhen added to the previous line offset, points to the nextline. In this way, the buffers may either be stored as linearblocks, or as logical blocks as desired.The Memory Organization Registers group consists of six32-bit registers located at GX_BASE+8310h-8328h.These registers are summarized in Table 4-28 on page141, and Table 4-30 gives their bit formats.Bit Name DescriptionTable 4-30. Display Controller Memory Organization RegistersGX_BASE+8310h-8313h DC_FB_ST_OFFSET Register (R/W) (Locked) Default Value = xxxxxxxxh31:22 RSVD Reserved: Set to 0.21:0 FB_START_OFFSETFrame Buffer Start Offset: This value represents the byte offset from the Graphics Base Address register(see GBADD of MC_GBASE_ADD register in Table 4-15 on page 116) of the starting location of thedisplayed frame buffer. This value may be changed to achieve panning across a virtual desktop or toallow multiple buffering.When this register is programmed to a nonzero value, the compression logic should be disabled. Thememory address defined by bits [21:4] will take effect at the start of the next frame scan. The pixel offsetdefined by bits [3:0] will take effect immediately (in general, it should only change during vertical blanking).GX_BASE+8314h-8317h DC_CB_ST_OFFSET Register (R/W) (Locked) Default Value = xxxxxxxxh31:22 RSVD Reserved: Set to 0.21:0 CB_START_OFFSETCompressed Display Buffer Start Offset: This value represents the byte offset from the GraphicsBase Address register (see GBADD of MC_GBASE_ADD register in Table 4-15 on page 116) of thestarting location of the compressed display buffer. Bits [3:0] must be programmed to zero so that thestart offset is aligned to a 16-byte boundary. This value should change only when a new display mode isset due to a change in size of the frame buffer.GX_BASE+8318h-831Bh DC_CUR_ST_OFFSET Register (R/W) (Locked) Default Value = xxxxxxxxh31:22 RSVD Reserved: Set to 0.21:0 CUR_START_OFFSETCursor Start Offset: This register contains the byte offset from the Graphics Base Address register (seeGBADD of MC_GBASE_ADD register in Table 4-15 on page 116) of the starting location of the cursordisplay pattern. Bits [1:0] should always be programmed to zero so that the start offset is DWORDaligned. The cursor data will be stored as a linear block of data.GX_BASE+831Ch-831Fh Reserved Default Value = 00000000hGX_BASE+8320h-8323h DC_VID_ST_OFFSET Register (R/W) (Locked) Default Value = xxxxxxxxh31:22 RSVD Reserved: Set to 0.21:0 VID_START_OFFSETVideo Buffer Start Offset Value: This register contains the byte offset from the Graphics Base Addressregister (see GBADD of MC_GBASE_ADD register in Table 4-15 on page 116) of the starting location ofthe Video Buffer Start. Bits [3:0] must be programmed as zero so that the start offset is aligned to a 16byte boundary.GX_BASE+8324h-8327h DC_LINE_DELTA Register (R/W) (Locked) Default Value = xxxxxxxxh31:22 RSVD Reserved: Set to 0.21:12 CB_LINE_DELTA11:10 RSVD Reserved: Set to 0.Compressed Display Buffer Line Delta: This value represents number of DWORDs that, when addedto the starting offset of the previous line, will point to the start of the next compressed line in memory. Itis used to always maintain a pointer to the starting offset for the compressed display buffer line beingloaded into the display FIFO.www.national.com 148 Revision 1.3
Integrated Functions (Continued)9:0 FB_LINE_DELTAFrame Buffer Line Delta: This value represents number of DWORDs that, when added to the startingoffset of the previous line, will point to the start of the next frame buffer line in memory. It is used toalways maintain a pointer to the starting offset for the frame buffer line being loaded into the displayFIFO.GX_BASE+8328h-832Bh DC_BUF_SIZE Register (R/W) (Locked) Default Value = xxxxxxxxh31:30 RSVD Reserved: Set to 0.29:16 VID_BUF_SIZE15:9 CB_LINE_SIZE8:0 FB_LINE_SIZETable 4-30. Display Controller Memory Organization Registers (Continued)Bit Name DescriptionVideo Buffer Size: These bits set the video buffer size, in 64-byte segments. The maximum size is 1MB.Compressed Display Buffer Line Size: This value represents the number of DWORDs for a valid compressedline plus 1. It is used to detect an overflow of the compressed data FIFO. It should never belarger than 41h since the maximum size of the compressed data FIFO is 64 DWORDs.FrameBufferLineSize:This value specifies the number of QWORDS (8-byte segments) to transfer foreach display line from the frame buffer.If panning is enabled, this value can generally be programmed to the displayed number of QWORDS + 2so that enough data is transferred to handle any possible alignment. Extra pixel data in the FIFO at theend of a line will automatically be discarded.Geode GXLV Processor SeriesGX_BASE+832Ch-832Fh Reserved Default Value = 00000000hRevision 1.3 149 www.national.com
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Geode GXLV Processor Series Low Pow
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Geode GXLV Processor Series Low Power Integrated x86 Solutions

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