Geode GXLV Processor Series Low Power Integrated x86 Solutions

More documents

Recommendations

Info

Geode GXLV Processor SeriesProcessor Programming (Continued)Bit Name DescriptionIndex B0h, B1h, B2h, B3h SMHR — SMM Header Address Register (R/W) Default Value = xxhIndex SMHR Bits SMM Header Address Bits [31:0]: SMHR address bits [31:0] contain the physical base address forthe SMM header space. For example, bits [31:24] correspond with Index B3h. Refer to Section 3.7.3“SMM Configuration Registers” on page 85 for more information.B3hB2hB1hB0hA[31:24]A[23:16]A[15:12]A[7:0]Note: MAPEN (CCR3[4]) must = 1 to read or write to this register.Index CDh, CEh, CFh SMAR — SMM Address Region/Size Register (R/W) Default Value = 00hIndex SMAR Bits SMM Address Region Bits [A31:A12]: SMAR address bits [31:12] contain the base address for theSMM region. For example, bits [31:24] correspond with index CDh. Refer to Section 3.7.3 “SMM ConfigurationRegisters” on page 85 for more information.CDhCEhCFh[7:4]A[31:24]A[23:16]A[15:12]Table 3-11. Configuration Registers (Continued)CFh[3:0] SIZE[3:0] SMM Region Size Bits [3:0]: SIZE address bits contain the size code for the SMM region. Duringaccess the lower 4-bits of Port 23h hold SIZE[3:0]. Index CFh allows simultaneous access to SMARaddress regions bits A[15:12] (see above) and size code bits SIZE[3:0].0000 = SMM Disabled 0100 = 32 KB 1000 = 512 KB 1100 = 8 MB0001 = 4 KB 0101 = 64 KB 1001 = 1 MB 1101 = 16 MB0010 = 8 KB 0110 = 128 KB 1010 = 2 MB 1110 = 32 MB0011 = 16 KB 0111 = 256 KB 1011 = 4 MB 1111 = 4 KB (same as 0001)Notes: 1. SMI_LOCK (CCR3[0]) must = 0, or the CPU must be in SMI mode, to write these registers/bits.2. Refer to Section 3.7.3 “SMM Configuration Registers” on page 85 for more information.Index FEh DIR0 — Device Identification Register 0 (RO) Default Value = 4xh7:4 DID[3:0] Device ID (Read Only): Identifies device as GXLV processor.3:0 MULT[3:0] Core Multiplier (Read Only): Identifies the core multiplier set by the CLKMODE[2:0] pins (see signaldescriptions page 31)MULT[3:0]:0000 = SYSCLK multiplied by 4 (Test mode only)0001 = SYSCLK multiplied by 100010 = SYSCLK multiplied by 40011 = SYSCLK multiplied by 60100 = SYSCLK multiplied by 90101 = SYSCLK multiplied by 50110 = SYSCLK multiplied by 70111 = SYSCLK multiplied by 81xxx = ReservedIndex FFh DIR1 — Device Identification Register 1 (RO) Default Value = xxh7:0 DIR1 Device Identification Revision (Read Only): DIR1 indicates device revision number.If DIR1 is 6xh = GXLV processor.www.national.com 54 Revision 1.3
Processor Programming (Continued)3.3.2.3 Debug RegistersSix debug registers (DR0-DR3, DR6 and DR7) supportdebugging on the GXLV processor. Memory addressesloaded in the debug registers, referred to as “breakpoints,”generate a debug exception when a memory access ofthe specified type occurs to the specified address. Abreakpoint can be specified for a particular kind of memoryaccess such as a read or write operation. Code anddata breakpoints can also be set allowing debug exceptionsto occur whenever a given data access (read or writeoperation) or code access (execute) occurs. The size ofthe debug target can be set to 1, 2, or 4 bytes. The debugregisters are accessed through MOV instructions that canbe executed only at privilege level 0 (real mode is alwaysprivilege level 0).The Debug Address Registers (DR0-DR3) each containthe linear address for one of four possible breakpoints.Each breakpoint is further specified by bits in the DebugControl Register (DR7). For each breakpoint address inDR0-DR3, there are corresponding fields L, R/W, andLEN in DR7 that specify the type of memory access associatedwith the breakpoint. DR6 is read only and reportsthe results of the break.The R/W field can be used to specify instruction executionas well as data access breakpoints. Instruction executionbreakpoints are always acted upon before execution ofthe instruction that matches the breakpoint. The DebugRegisters are mapped in Table 3-12, and the bit definitionsare given in Table 3-13 on page 56.Geode GXLV Processor SeriesTable 3-12. Debug Registers31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0DR7 RegisterDebug Control Register 7 (R/W)LEN3 R/W3 LEN2 R/W2 LEN1 R/W1 LEN0 R/W0 0 0 GD0 0 1 0 0 G3DR6 RegisterDebug Status Register 6 (R/O)0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BTBS0 1 1 1 1 1 1 1 1 1 B3 B2 B1 B0DR3 RegisterDebug Address Register 3 (R/W)Breakpoint 3 Linear AddressDR2 RegisterDebug Address Register 2 (R/W)Breakpoint 2 Linear AddressDR1 RegisterDebug Address Register 1 (R/W)Breakpoint 1 Linear AddressDR0 RegisterDebug Address Register 0 (R/W)Breakpoint 0 Linear AddressNote: All bits marked as 0 or 1 are reserved and should not be modified.L3G2L2G1L1G0L0Revision 1.3 55 www.national.com
Page 4 and 5: Geode GXLV Processor SeriesTable of
Page 6 and 7: Geode GXLV Processor SeriesTable of
Page 8: Geode GXLV Processor SeriesTable of
Page 12 and 13: Geode GXLV Processor SeriesArchitec
Page 15 and 16: Architecture Overview (Continued)Ge
Page 17 and 18: Architecture Overview (Continued)SD
Page 19 and 20: 2.0 Signal DefinitionsThis section
Page 21 and 22: Signal Definitions (Continued)Index
Page 23 and 24: Signal Definitions (Continued)PinNo
Page 25 and 26: Signal Definitions (Continued)Table
Page 27 and 28: Signal Definitions (Continued)PinNo
Page 29 and 30: Signal Definitions (Continued)Table
Page 31 and 32: Signal Definitions (Continued)2.2 S
Page 33 and 34: Signal Definitions (Continued)2.2.2
Page 41 and 42: 3.0 Processor ProgrammingThis secti
Page 43 and 44: Processor Programming (Continued)3.
Page 49 and 50: Processor Programming (Continued)Bi
Page 51 and 52: Processor Programming (Continued)Ta
Page 53: Processor Programming (Continued)Bi
Page 61 and 62: Processor Programming (Continued)Th
Page 65 and 66: Processor Programming (Continued)Ad
Page 69 and 70: Processor Programming (Continued)Se
Page 73 and 74: Processor Programming (Continued)TY
Page 75 and 76: Processor Programming (Continued)Ta
Page 89 and 90: Processor Programming (Continued)Wh
Page 95 and 96: Processor Programming (Continued)Bi
Page 97 and 98: Integrated Functions (Continued)4.1
Page 101 and 102: Integrated Functions (Continued)Mne
Page 105 and 106:
Integrated Functions (Continued)Bit
Page 107 and 108:
Integrated Functions (Continued)4.3
Page 109 and 110:
Page 111 and 112:
Integrated Functions (Continued)ACT
Page 113 and 114:
Page 115 and 116:
Page 117 and 118:
Page 119 and 120:
Integrated Functions (Continued)Tab
Page 121 and 122:
Integrated Functions (Continued)SDR
Page 123 and 124:
Page 125 and 126:
Page 127 and 128:
Page 129 and 130:
Page 131 and 132:
Page 133 and 134:
Page 135 and 136:
Page 137 and 138:
Integrated Functions (Continued).Re
Page 139 and 140:
Integrated Functions (Continued)640
Page 141 and 142:
Page 143 and 144:
Integrated Functions (Continued)GX_
Page 145 and 146:
Integrated Functions (Continued)11:
Page 147 and 148:
Page 149 and 150:
Integrated Functions (Continued)9:0
Page 151 and 152:
Page 153 and 154:
Page 155 and 156:
Page 157 and 158:
Page 159 and 160:
Page 161 and 162:
Page 163 and 164:
Page 165 and 166:
Page 167 and 168:
Page 169 and 170:
Page 171 and 172:
Page 173 and 174:
Page 175 and 176:
Page 177 and 178:
Power Management (Continued)CPU Sus
Page 179 and 180:
Power Management (Continued)5.2.2 I
Page 181 and 182:
Power Management (Continued)5.3 POW
Page 183 and 184:
Power Management (Continued)Table 5
Page 185 and 186:
Electrical Specifications (Continue
Page 187 and 188:
Page 189 and 190:
Page 191 and 192:
Page 193 and 194:
Page 195 and 196:
Page 197 and 198:
Page 199 and 200:
Page 201 and 202:
Page 203 and 204:
Page 205 and 206:
Page 207 and 208:
7.0 Instruction SetThis section sum
Page 209 and 210:
Instruction Set (Continued)7.1.2.3
Page 211 and 212:
Page 213 and 214:
Page 215 and 216:
Page 217 and 218:
Instruction Set (Continued)Table 7-
Page 219 and 220:
Instruction Set (Continued)Instruct
Page 221 and 222:
Instruction Set (Continued)JMP Unco
Page 223 and 224:
Page 225 and 226:
Page 227 and 228:
Page 229 and 230:
Page 231 and 232:
Page 233 and 234:
Instruction Set (Continued)7.5 MMX
Page 235 and 236:
Instruction Set (Continued)PCMPEQB
Page 237 and 238:
Instruction Set (Continued)PUNPCKHW
Page 239 and 240:
Page 241 and 242:
Package Specifications (Continued)C
Page 243 and 244:
Package Specifications (Continued)8
Page 245 and 246:
Package Specifications (Continued)S
Page 247:
Geode GXLV Processor Series Low Pow
show all

Geode GXLV Processor Series Low Power Integrated x86 Solutions

Create successful ePaper yourself

Delete template?

Save as template?