Geode GXLV Processor Series Low Power Integrated x86 Solutions

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Geode GXLV Processor SeriesSignal Definitions (Continued)2.2.6 Internal Test and Measurement Signals (Continued)Signal NameTMSTESTBGAPin No.H1(PU)F3(PD)SPGAPin No. Type DescriptionN3(PU)J5(PD)IITest Mode SelectJTAG test-mode select.This pin is internally connected to a weak (>20-kohm) pull-upresistor.TestTest-mode input.This pin is internally connected to a weak (>20-kohm) pull-upresistor.www.national.com 40 Revision 1.3
3.0 Processor ProgrammingThis section describes the internal operations of theGeode GXLV processor from a programmer’s point ofview. It includes a description of the traditional “core” processingand FPU operations. The integrated function registersare described at the end of this chapter.The primary register sets within the processor coreinclude:• Application Register Set• System Register Set• Model Specific Register SetThe initialization of the major registers within the core areshowninTable3-1.Theintegratedfunctionsetsarelocatedinmainmemoryspace and include:• Internal Bus Interface Unit Register Set• Graphics Pipeline Register Set• Display Controller Register Set• Memory Controller Register Set• Power Management Register Set3.1 CORE PROCESSOR INITIALIZATIONThe GXLV processor is initialized when the RESET signalis asserted. The processor is placed in real mode and theregisters listed in Table 3-1 are set to their initialized values.RESET invalidates and disables the CPU cache, andturns off paging. When RESET is asserted, the CPU terminatesall local bus activity and all internal execution.While RESET is asserted the internal pipeline is flushedand no instruction execution or bus activity occurs.Approximately 150 to 250 external clock cycles afterRESET is deasserted, the processor begins executinginstructions at the top of physical memory (address locationFFFFFFF0h). The actual number of clock cyclesdepends on the clock scaling in use. Also, before executionbegins, an additional 2 20 clock cycles are neededwhen self-test is requested.Typically, an intersegment jump is placed at FFFFFFF0h.This instruction will force the processor to begin executionin the lowest 1 MB of address space.Table 3-1 lists the core registers and illustrates how theyare initialized.Geode GXLV Processor SeriesTable 3-1. Initialized Core Register ControlsRegister Register Name Initialized Contents CommentsEAX Accumulator xxxxxxxxh 0000 0000h indicates self-test passed.EBX Base xxxxxxxxhECX Count xxxxxxxxhEDX Data xxxx 04 [DIR0]h DIR0 = Device IDEBP Base Pointer xxxxxxxxhESI Source Index xxxxxxxxhEDI Destination Index xxxxxxxxhESP Stack Pointer xxxxxxxxhEFLAGS Flags 00000002h See Table 3-4 on page 46 for bit definitions.EIP Instruction Pointer 0000FFF0hES Extra Segment 0000h Base address set to 00000000h. Limit set to FFFFh.CS Code Segment F000h Base address set to FFFF0000h. Limit set to FFFFh.SS Stack Segment 0000h Base address set to 00000000h. Limit set to FFFFh.DS Data Segment 0000h Base address set to 00000000h. Limit set to FFFFh.FS Extra Segment 0000h Base address set to 00000000h. Limit set to FFFFh.GS Extra Segment 0000h Base address set to 00000000h. Limit set to FFFFh.IDTR Interrupt Descriptor Table Register Base = 0, Limit = 3FFhGDTR Global Descriptor Table Register xxxxxxxxhLDTR Local Descriptor Table Register xxxxhTR Task Register xxxxhCR0 Control Register 0 60000010h See Table 3-7 on page 49 for bit definitions.CR2 Control Register 2 xxxxxxxxh See Table 3-7 on page 49 for bit definitions.CR3 Control Register 3 xxxxxxxxh See Table 3-7 on page 48 for bit definitions.CR4 Control Register 4 00000000h See Table 3-7 on page 48 for bit definitions.CCR1 Configuration Control 1 00h See Table 3-11 on page 52 for bit definitions.CCR2 Configuration Control 2 00h See Table 3-11 on page 52 for bit definitions.CCR3 Configuration Control 3 00h See Table 3-11 on page 52 for bit definitions.CCR4 Configuration Control 4 00h See Table 3-11 on page 52 for bit definitions.CCR7 Configuration Control 7 00h See Table 3-11 on page 52 for bit definitions.Revision 1.3 41 www.national.com
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Geode GXLV Processor Series Low Pow
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Geode GXLV Processor Series Low Power Integrated x86 Solutions

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