Geode GXLV Processor Series Low Power Integrated x86 Solutions

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Geode GXLV Processor SeriesIntegrated Functions (Continued)4.7.7 PCI Configuration Space RegistersTo access the internal PCI configuration registers of theGXLV processor, the Configuration Address Register(CONFIG_ADDRESS) must be written as a DWORDusing the format shown in Table 4-42. Any other size willbeinterpretedasanI/OwritetoPort0CF8h.Also,whenentering the Configuration Index, only the six most significantbits of the offset are used, and the two least significantbits must be 00b.Table 4-43 summarizes the registers located within theConfiguration Space. The tables that follow, give detailedregister/bit formats.Table 4-42. Format for Accessing the Internal PCI Configuration Registers31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 01 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Configuration Index 0 0Table 4-43. PCI Configuration Space Register SummaryIndex Type Name/Function Default Value00h-01h RO Vendor Identification 1078h02h-03h RO Device Identification 0001h04h-05h R/W PCI Command 0007h06h-07h R/W Device Status 0280h08h RO Revision Identification 00h09h-0Bh RO Class Code 060000h0Ch RO Cache Line Size 00h0Dh R/W Latency Timer 00h0Eh-3Fh -- Reserved 00h40h R/W PCI Control Function 1 00h41h R/W PCI Control Function 2 96h42h -- Reserved 00h43h R/W PCI Arbitration Control 1 80h44h R/W PCI Arbitration Control 2 00h45h-FFh -- Reserved 00hwww.national.com 168 Revision 1.3
Integrated Functions (Continued)Bit Name DescriptionTable 4-44. PCI Configuration RegistersIndex 00h-01h Vendor Identification Register (RO) Default Value = 1078h31:0 VID (RO) Vendor Identification Register (Read Only): The combination of this value and the device ID uniquelyidentifies any PCI device. The Vendor ID is the ID given to National Semiconductor Corporation by thePCI SIG.Index 02h-03h Device Identification Register (RO) Default Value = 0001h31:0 DIR (RO) Device Identification Register (Read Only): This value along with the vendor ID uniquely identifies anyPCI device.Index 04h-05h PCI Command Register (R/W) Default Value = 0007h15:10 RSVD Reserved: Set to 0.9 FBE Fast Back-to-Back Enable (RO): As a master, the GXLV processor does not support this function.This bit returns 0.8 SERR SERR# Enable: This is used as an output enable gate for the SERR# driver.7 WAT Wait Cycle Control: GXLV processor does not do address/data stepping.This bit is always set to 0.6 PE Parity Error Response:0 = GXLV processor ignores parity errors on the PCI bus.1 = GXLV processor checks for parity errors.5 VPS VGA Palette Snoop: GXLV processor does not support this function.This bit is always set to 0.4 MS Memory Write and Invalidate Enable: As a master, the GXLV processor does not support this function.This bit is always set to 0.3 SPC Special Cycles: GXLV processor does not respond to special cycles on the PCI bus.This bit is always set to 0.2 BM Bus Master:0 = GXLV processor does not perform master cycles on the PCI bus.1 = GXLV processor can act as a bus master on the PCI bus.1 MS Memory Space: GXLV processor will always respond to memory cycles on the PCI bus.This bit is always set to 1.0 IOS I/O Space: GXLV processor will not respond to I/O accesses from the PCI bus.This bit is always set to 1.Geode GXLV Processor SeriesIndex 06h-07h PCI Device Status Register (RO, R/W Clear) Default Value = 0280h15 DPE Detected Parity Error: When a parity error is detected, this bit is set to 1.This bit can be cleared to 0 by writing a 1 to it.14 SSE Signaled System Error: This bit is set whenever SERR# is driven active.13 RMA Received Master Abort: This bit is set whenever a master abort cycle occurs. A master abort will occurwhenever a PCI cycle is not claimed except for special cycles.This bit can be cleared to 0 by writing a 1 to it.12 RTA Received Target Abort: This bit is set whenever a target abort is received while the GXLV processor ismaster of the cycle.This bit can be cleared to 0 by writing a 1 to it.11 STA Signaled Target Abort: This bit is set whenever the GXLV processor signals a target abort. A targetabort is signaled when an address parity occurs for an address that hits in the GXLV processor’saddress space.This bit can be cleared to 0 by writing a 1 to it.10:9 DT Device Timing: The GXLV processor performs medium DEVSEL# active for addresses that hit into theGXLV processor address space. These two bits are always set to 01.00 = Fast01 = Medium10 = Slow11 = ReservedRevision 1.3 169 www.national.com
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Geode GXLV Processor Series Low Pow
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