Geode GXLV Processor Series Low Power Integrated x86 Solutions

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Geode GXLV Processor SeriesIntegrated Functions (Continued)4.5.7 Graphics Memory MapThe GXLV processor supports a maximum of 4 MB ofgraphics memory and will map it to an address space (seeFigure 4-2 on page 98) higher than the maximum amountof installed RAM. The graphics memory aperture physicallyresides at the top of the installed system RAM. Thestart address and size of the graphics memory apertureare programmable on 512 KB boundaries. Typically, thesystem BIOS sets the size and start address of the graphicsmemory aperture during the boot process based onthe amount of installed RAM, user defined CMOS settings,hard coded, etc. The graphics pipeline and displaycontroller address the graphics memory with a 20-bit offset(address bits [21:2]) and four byte enables into thegraphics memory aperture. The graphics memory storesseveral buffers that are used to generate the display: theframe buffer, compressed display buffer, VGA memory,and cursor pattern(s). Any remaining off-screen memorywithin the graphics aperture may be used by the displaydriver as desired or not at all.4.5.7.1 DC Memory Organization RegistersThe display controller contains a number of registers thatallow full programmability of the graphics memory organization.This includes starting offsets for each of the bufferregions described above, line delta parameters for theframe buffer and compression buffer, as well as compressedline-buffer size information. The starting offsetsfor the various buffers are programmable for a highdegree of flexibility in memory organization.4.5.7.2 Frame Buffer and Compression Buffer OrganizationThe GXLV processor supports primary display modes640x480, 800x600, and 1024x768 at both 8-bpp and 16-bpp, and 1280x1024 at 8-bpp. Pixels are packed intoDWORDs as shown in Figure 4-15.In order to simplify address calculations by the renderinghardware, the frame buffer is organized in an XY fashionwhere the offset is simply a concatenation of the X and Ypixel addresses. All 8-bpp display modes with the exceptionof the 1280x1024 resolution will use a 1024-byte linedelta between the starting offsets of adjacent lines. All 16-bpp display modes and 1280x1024x8-bpp display modeswill use a 2048-byte line delta between the starting offsetsof adjacent lines. If there is room, the space between theend of a line and the start of the next line will be filled withthe compressed display data for that line, thus allowingefficient memory utilization. For 1024x768 display modes,theframe-bufferlinesizeisthesameasthelinedelta,sono room is left for the compressed display data betweenlines. In this case, the compressed display buffer beginsat the end of the frame buffer region and is linearlymapped.(0, 0)8-bpp up to 1024x768DWORD 0DWORD 1(1023,0)(0, 0)16-bpp up to 1024x7688-bpp up to 1280x1024DWORD 0 DWORD 1... ...(2047,0)(0, 1023)(1023, 1023)(0, 1023)(2047, 1023)DWORDBit Position 31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0Address 3h 2h 1h 0hPixel Org - 8-bpp (3,0) (2,0) (1,0) (0,0)Pixel Org - 16-bpp (1,0) (0,0)Figure 4-15. Pixel Arrangement Within a DWORDwww.national.com 140 Revision 1.3
Integrated Functions (Continued)4.5.7.3 VGA Display SupportThe graphics pipeline contains full hardware support fortheVGAfrontend.TheVGAdataisstoredina256KBbuffer located in graphics memory. The main task for VirtualVGA (see Section 4.6 “Virtual VGA Subsystem” onpage 157) is converting the data in the VGA buffer to an 8-bpp frame buffer that can be displayed by the display controller.For some modes, the display controller can display theVGA data directly and the data conversion is not necessary.This includes standard VGA mode 13h and the variationsof that mode used in several games; the displaycontroller can also directly display VGA planar graphicsmodes D, E, F, 10, 11, and 12. Likewise, the hardware candirectly display all of the higher-resolution VESA modes.Since the frame buffer data is written directly to memoryinstead of travelling across an external bus, the GXLV processoroften outperforms VGA cards for these modes.The display controller, however, does not directly supporttext modes. SoftVGA must convert the characters andattributes in the VGA buffer to an 8-bpp frame bufferimage the hardware uses for display refresh.4.5.8 Display Controller RegistersThe Display Controller maps 100h memory locationsstarting at GX_BASE+8300h for the display controller registers.Refer to Section 4.1.2 “Control Registers” on page99 for instructions on accessing these registers.The Display Controller Registers are divided into six categories:• Configuration and Status Registers• Memory Organization Registers• Timing Registers• Cursor and Line Compare Registers• Color Registers• Palette and RAM Diagnostic RegistersTable 4-28 summarizes these registers and locations, andthe following subsections give detailed register/bit formats.Geode GXLV Processor SeriesTable 4-28. Display Controller Register SummaryGX_BASE+Memory Offset Type Name/FunctionDefaultValueConfiguration and Status Registers8300h-8303h R/W DC_UNLOCKDisplay Controller Unlock: This register is provided to lock the most critical memorymappeddisplay controller registers to prevent unwanted modification (write operations).Read operations are always allowed.8304h-8307h R/W DC_GENERAL_CFGDisplay Controller General Configuration: General control bits for the display controller.8308h-830Bh R/W DC_TIMING_CFGDisplay Controller Timing Configuration: Status and control bits for various displaytiming functions.830Ch-830Fh R/W DC_OUTPUT_CFGDisplay Controller Output Configuration: Status and control bits for pixel outputformatting functions.00000000h00000000hxx000000hxx000000hMemory Organization Registers8310h-8313h R/W DC_FB_ST_OFFSETDisplay Controller Frame Buffer Start Address: Specifies offset at which the frame bufferstarts.8314h-8317h R/W DC_CB_ST_OFFSETDisplay Controller Compression Buffer Start Address: Specifies offset at which the compresseddisplay buffer starts.8318h-831Bh R/W DC_CUR_ST_OFFSETDisplay Controller Cursor Buffer Start Address: Specifies offset at which the cursor memorybuffer starts.xxxxxxxxhxxxxxxxxhxxxxxxxxh831Ch-831Fh -- Reserved 00000000h8320h-8323h R/W DC_VID_ST_OFFSETxxxxxxxxhDisplay Controller Video Start Address: Specifies offset at which the video buffer starts.8324h-8327h R/W DC_LINE_DELTADisplay Controller Line Delta: Stores line delta for the graphics display buffers.xxxxxxxxhRevision 1.3 141 www.national.com
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Geode GXLV Processor Series Low Pow
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Geode GXLV Processor Series Low Power Integrated x86 Solutions

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