Geode GXLV Processor Series Low Power Integrated x86 Solutions

Geode GXLV Processor SeriesIntegrated Functions (Continued)The SDRAM interface timings are programmable. TheSHFTSDCLK bits in the MC_MEM_CNTRL2 register canbe used to change the relationship between SDCLK andthe control/address/data signals to meet setup and holdtime requirements for SDRAM across different board layouts.SHFTSDCLK bit values are selected based upon theSDRAM signals loads and the core frequency (refer toFigures 6-9 and 6-10 on page 202).Figure 4-10 shows an example of how the SHFTSDCLKbits setting affects SDCLK. The PCI clock is the inputclock to the GXLV processor. The core clock is the internalprocessor clock that is multiplied up. The memory controllerruns off this core clock. The memory clock is generatedby dividing down the core clock. SDCLK is generatedfrom the memory clock. In the example diagram, the processorclock is running 6X times the PCI clock and thememory clock is running in divide by 3 mode.The SDRAM control, address, and data signals are drivenoff edge “x 1 ” of the memory clock to be setup before edge“y 1 ”. With no shift applied, the control signals could end upbeing latched on edge “x 2 ” of the SDCLK. A shift value oftwo or three could be used so that SDCLK at the SDRAMis centered around when the control signals change.PCI ClockCore Clock(Internal)MemoryClock(Internal)0 1 2 3 4 5 6x 1 y 1CNTRLValidSDCLK(Note)x 2 y 2SDCLK(Note)Shift =4321 0Note: The first SDCLK shows how SDCLK operates with the SHFTSDCLK bits = 000, no shift.The second SDCLK shows how SDCLK operates with the SHFTSDCLK bits = 001, shift 0.5 core clock.(See MC_MEMCNTRL2 bits [5:3], Table 4-15 on page 114, for remaining decode values.)Figure 4-10. Effects of SHFTSDCLK Programming Bits Examplewww.national.com 124 Revision 1.3