Geode GXLV Processor Series Low Power Integrated x86 Solutions

Integrated Functions (Continued)4.3.7 SDRAM Interface ClockingTheGXLVprocessordrivestheSDCLKtotheSDRAMs;one for each DIMM bank. All the control, data, andaddress signals driven by the memory controller are sampledby the SDRAM at the rising edge of SDCLK. SDCLK-OUT is a reference signal used to generate SDCLKIN.Read data is sampled by the memory controller at the risingedge of SDCLKIN.SDCLK[3:0]The delay for SDCLKIN from SDCLKOUT must bedesigned so that it lags the SDCLKs at the DRAM byapproximately 1 ns (check application notes for additionalinformation). The delay should also include the SDCLKtransmission line delay. All four SDCLK traces on theboard should be the same length, so there is no skewbetween them. These guidelines allow the memory interfaceto operate at a higher performance.SDCLK0SDCLK1DIMM0Geode GXLV Processor SeriesSDCLKOUTSDCLK2Geode GXLVProcessorDelaySDCLK3DIMM1SDCLKINFigure 4-9. SDCLKIN ClockingRevision 1.3 123 www.national.com