Geode GXLV Processor Series Low Power Integrated x86 Solutions

Geode GXLV Processor SeriesSignal Definitions (Continued)2.2.2 PCI Interface Signals (Continued)Signal NameAD[31:0]BGAPin No.RefertoTable 2-3SPGAPin No Type DescriptionRefertoTable 2-5I/OMultiplexed Address and DataAddresses and data are multiplexed together on the same pins.A bus transaction consists of an address phase in the cycle inwhich FRAME# is asserted followed by one or more dataphases. During the address phase, AD[31:0] contain a physical32-bit address. During data phases, AD[7:0] contain the leastsignificant byte (LSB) and AD[31:24] contain the most significantbyte (MSB). Write data is stable and valid when IRDY# isasserted and read data is stable and valid when TRDY# isasserted. Data is transferred during the SYSCLK when bothIRDY# and TRDY# are asserted.C/BE[3:0]# D5, B6, I/O Multiplexed Command and Byte EnablesB8, B12,C/BE# are the bus commands and byte enables. They are multiplexedtogether on the same PCI pins. During the address phaseC13, A15 B18, E21of a transaction when FRAME# is active, C/BE[3:0]# define thebus command. During the data phase C/BE[3:0]# are used asbyte enables. The byte enables are valid for the entire dataphase and determine which byte lanes carry meaningful data.C/BE0# applies to byte 0 (LSB) and C/BE3# applies to byte 3(MSB).The command encoding and types are listed below.0000 = Interrupt Acknowledge0001 = Special Cycle0010 = I/O Read0011 = I/O Write0100 = Reserved0101 = Reserved0110 = Memory Read0111 = Memory Write1000 = Reserved1001 = Reserved1010 = Configuration Read1011 = Configuration Write1100 = Memory Read Multiple1101 = Dual Address Cycle (Reserved)1110 = Memory Read Line1111 = Memory Write and InvalidatePAR B12 C17 I/O ParityPARisusedwithAD[31:0]andC/BE[3:0]#togenerateevenparity.Parity generation is required by all PCI agents: the masterdrives PAR for address and write-data phases, the target drivesPAR for read-data phases.For address phases, PAR is stable and valid one SYSCLK afterthe address phase.For data phases, PAR is stable and valid one SYSCLK aftereither IRDY# is asserted on a write transaction or after TRDY# isasserted on a read transaction. Once PAR is valid, it remainsvalid until one SYSCLK after the completion of the data phase.(Also see PERR# description on page 35.)www.national.com 34 Revision 1.3