Geode GXLV Processor Series Low Power Integrated x86 Solutions

Geode GXLV Processor SeriesPower Management (Continued)Table 5-2. Power Management Control and Status Registers (Continued)Bit Name DescriptionGX_BASE+8504h-8507h PM_CNTRL_TEN Register (R/W) Default Value = xxxxxx00h31:8 RSVD Reserved: These bits are not used. Do not write to these bits.7:6 RSVD Reserved: Set to 0.5 X_TEST (WO) Transmission Test (Write Only) : Setting this bit causes the GXLV processor to immediately transmitthe current contents of the serial packet. This bit is write only and is used primarily for test. Thisbit returns 0 on a read.4:3 X_FREQ Transmission Frequency: This field indicates the time between serial packet transmissions. Serialpacket transmissions occur at the selected interval only if at least one of the packet bits is set high:00 = Disable transmitter; 01 = 1 ms; 10 = 5 ms; 11 = 10 ms.2 CPU_RD CPU Activity Read Enable: Setting this bit high enables reporting of CPU level-1 cache readmisses that are not a result of an instruction fetch. This bit is a don’t-care if the CPU_EN bit is not sethigh.1 CPU_EN CPU Activity Master Enable: Setting this bit high enables reporting of CPU Level-1 cache missesin bit 6 of the serial transmission packet. When enabled, the CPU Level-1 cache miss activity isreported on any read (assuming the CPU_RD is set high) or write access excluding misses thatresulted from an instruction fetch.0 VID_EN Video Event Enable: Setting this bit high enables video decode events to be reported in bit 0 of theserial transmission packet. CPU or graphics-pipeline accesses to the graphics memory and displaycontroller-registeraccesses are also reported.GX_BASE+8508h-850Bh PM_CNTRL_CSTP Register (R/W) Default Value = xxxxxx00h31:8 RSVD Reserved: These bits are not used. Do not write to these bits.7:1 RSVD Reserved: Set to 0.0 CLK_STP Clock Stop: This bit configures the GXLV processor for Suspend Refresh Mode or 3 Volt SuspendMode:0 = Suspend Refresh Mode. The clocks to the memory and display controller remain active duringSuspend.1 = 3 Volt Suspend Mode. The external clock may be stopped during Suspend.Note: When bit 0 is set high and the Suspend input pin (SUSP#) is asserted, the GXLV processor stops all it’s internal clocks, andasserts the Suspend Acknowledge output pin (SUSPA#). Once SUSPA# is asserted the GXLV processor’s SYSCLK input canbe stopped. If bit 0 is cleared, the internal memory-controller and display-controller clocks are not stopped on theSUSP#/SUSPA# sequence, and the SYSCLK input can not be stopped.GX_BASE+850Ch-850Fh PM_SER_PACK Register (R/O) Default Value = xxxxxx00h31:8 RSVD Reserved: These bits are not used. Do not write to these bits.7 VID_IRQ Video IRQ: This bit indicates the occurrence of a video vertical sync pulse. This bit is set at thesame time that the VINT (Vertical Interrupt) bit is set in the DC_TIMING_CFG register. The VINT bithas a corresponding enable bit (VIEN) in the DC_TIM_CFG register (See Table 4-29 on page 145).6 CPU_ACT CPU Activity: This bit indicates the occurrence of a level 1 cache miss that was not a result of aninstruction fetch. This bit has a corresponding enable bit in the PM_CNTL_TEN register.5:2 RSVD Reserved: Set to 0.1 USR_DEF Programmable Address Decode: This bit indicates the occurrence of a programmable memoryaddress decode. This bit is set based on the values of the PM_BASE register and the PM_MASKregister (see Table 5-3 on page 183). The PM_BASE register can be initialized to any address in thefull 256 MB address range.0 VID_DEC Video Decode: This bit indicates that the CPU has accessed either the Display Controller registersor the graphics memory region. This bit has a corresponding enable bit in the PM_CNTRL_TEN.Note: The GXLV processor transmits the contents of the serial packet only when a bit in the packet register is set and the intervalcounter has elapsed. The Geode I/O companion decodes the serial packet after each transmission. Once a bit in the packet isset, it will remain set until the completion of the next packet transmission. Successive events of the same type that occurbetween packet transmissions are ignored. Multiple unique events between packet transmissions will accumulate in this register.www.national.com 182 Revision 1.3