Geode GXLV Processor Series Low Power Integrated x86 Solutions

Geode GXLV Processor SeriesProcessor Programming (Continued)Bit Name DescriptionTable 3-17. TR5-TR3 Bit DefinitionsTR5 Register (R/W)31:12 RSVD Reserved11:4 Line Selection Line Selection:Physical address bits [11:4] used to select one of 256 lines.3:2 Set/DWORDSelectionSet/DWORD Selection:Cache read: Selects which of the four sets in the cache is used as the source for datatransferred to the cache flush buffer.Cache write: Selects which of the four sets in the cache is used as the destination for data transferredfrom the cache fill buffer.Flush buffer read: Selects which of the four DWORDs in the flush buffer is used during a TR3 read.Fill buffer write: Selects which of the four DWORDs in the fill buffer is written during a TR3 write.1:0 Control Bits Control Bits:00 = Flush read or fill buffer write.01 = Cache write.10 = Cache read.11 = Cache flush.TR4 Register (R/W)31:12 Upper TagAddressUpper Tag Address:Cache read: Upper 20 bits of tag address of the selected entry.Cache write: Data written into the upper 20 bits of the tag address of the selected entry.10 Valid Bit Valid Bit:Cache read: Valid bit for the selected entry.Cache write: Data written into the valid bit for the selected entry.9:7 LRU Bits LRU Bits:Cache read: The LRU bits for the selected line when scratchpad is disabled.xx1 = Set 0 or Set 1 most recently accessed.xx0 = Set 2 or Set 3 most recently accessed.x1x = Most recent access to Set 0 or Set 1 was to Set 0.x0x = Most recent access to Set 0 or Set 1 was to Set 1.1xx = Most recent access to Set 2 or Set 3 was to Set 2.0xx = Most recent access to Set 2 or Set 3 was to Set 3.Cache write: Ignored.6:3 Dirty Bits Dirty Bits:Cache read: The dirty bits for the selected entry (one bit per DWORD).Cache write: Data written into the dirty bits for the selected entry.2:0 RSVD Reserved: Set to 0.TR3 Register (R/W)31:0 Cache Data Cache Data:Flush buffer read: Data accessed from the cache flush buffer.Fill buffer write: Data to be written into the cache fill buffer.www.national.com 60 Revision 1.3