Geode GXLV Processor Series Low Power Integrated x86 Solutions

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Geode GXLV Processor SeriesProcessor Programming (Continued)3.7.1 SMM OperationSMM execution flow is summarized in Figure 3-10. EnteringSMM requires the assertion of the SMI# pin for at leasttwo SYSCLK periods or execution of the SMINT instruction.For the SMI# signal or SMINT instruction to be recognized,the following configuration registers must be programmed:• SMAR (Index CDh-CFh) - The SMM Base address andsize.• CCR1 (Index C1) - SMAC bit and/or USE_SMI bit.These registers formats are given in Table 3-11 on page52.After triggering an SMM through the SMI# pin or a SMINTinstruction, selected CPU state information is automaticallysaved in the SMM memory space header located atthe top of SMM memory space. After saving the header,the CPU enters real mode and begins executing the SMMservice routine starting at the SMM memory region baseaddress.The SMM service routine is user definable and may containsystem or power management software. If the powermanagement software forces the CPU to power down or ifthe SMM service routine modifies more registers than areautomatically saved, the complete CPU state informationshould be saved.SMI# Sampled Active orSMINT Instruction ExecutedCPU State Stored in SMMAddress Space HeaderProgram Flow Transfersto SMM Address SpaceCPU Enters Real ModeExecution Begins at SMMAddress Space Base AddressRSM Instruction Restores CPUState Using Header InformationNormal Execution ResumesFigure 3-10. SMM Execution Flowwww.national.com 84 Revision 1.3
Processor Programming (Continued)3.7.2 SMI# PinExternal chipsets can generate an SMI based on numerousasynchronous events, including power managementtimers, I/O address trapping, external devices, audio FIFOevents, and others. Since SMI# is edge sensitive, thechipset must generate an edge for each of the eventsabove, requiring arbitration and storage of multiple SMMevents. These functions are provided by the CS5530 I/Ocompanion device. The processor generates an SMIwhen the external pin changes from high-to-low or whenan Resume (RSM) occurs if SMI# has not remained lowsince the initiation of the previous SMI.3.7.3 SMM Configuration RegistersThe SMAR register specifies the base location of SMMcode region and its size limit.The SMHR register specifies the 32-bit physical addressof the SMM header. The SMHR address must be 32-bitaligned as the bottom two bits are ignored by the microcode.Hardware will detect write operations to SMAR, andsignal the microcode to recompute the header address.Access to the SMAR and SMHR registers is enabled byMAPEN (Index C3h[4] see bit details on page 52).The SMAR register writes to the SMHR register when theSMAR register is changed. For this reason, changes tothe SMAR register should be completed prior to setting upthe SMHR register. The configuration registers bit formatsare detailed in Table 3-11 beginning on page 52.3.7.4 SMM Memory Space HeaderTables 3-34 and 3-35 show the SMM header. A memoryaddress field has been added to the end (offset -40h) ofthe header for the GXLV processor. Memory data will bestored overlapping the I/O data, since these events cannotoccur simultaneously. The I/O address is valid for bothIN and OUT instructions, and I/O data is valid only forOUT. The memory address is valid for read and writeoperations, and memory data is valid only for write operations.With every SMI interrupt or SMINT instruction, selectedCPU state information is automatically saved in the SMMmemory space header located at the top of SMM addressspace. The header contains CPU state information that ismodified when servicing an SMM interrupt. Included inthis information are two pointers. The Current IP points tothe instruction executing when the SMI was detected, butit is valid only for an internal I/O SMI.The Next IP points to the instruction that will be executedafter exiting SMM. The contents of Debug Register 7(DR7), the Extended Flags Register (EFLAGS), and ControlRegister 0 (CR0) are also saved. If SMM has beenentered due to an I/O trap for a REP INSx or REP OUTSxinstruction, the Current IP and Next IP fields contain thesame addresses. In addition, the I and P fields containvalid information.If entry into SMM is the result of an I/O trap, it is useful forthe programmer to know the port address, data size anddata value associated with that I/O operation. This informationis also saved in the header and is valid only if SMI# isasserted during an I/O bus cycle. The I/O trap information isnot restored within the CPU when executing a RSM instruction.Geode GXLV Processor SeriesTable 3-34. SMM Memory Space HeaderMem.Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0-04h DR7–08h EFLAGS–0ChCR0–10h Current IP–14h Next IP–18h RSVD CS Selector–1Ch CS Descriptor [63:32]–20h CS Descriptor [31:0]–24h RSVD RSVD N V X M H S P I C–28h I/O Data Size I/O Address [15:0]–2Ch I/O or Memory Data [31:0]–30h Restored ESI or EDI–34h I/O or Memory Address [31:0]Note: Check the M bit at offset 24 h to determine if the data is memory or I/O.Revision 1.3 85 www.national.com
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2.0 Signal DefinitionsThis section
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Signal Definitions (Continued)PinNo
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Signal Definitions (Continued)PinNo
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Geode GXLV Processor Series Low Pow
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Geode GXLV Processor Series Low Power Integrated x86 Solutions

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