Geode GXLV Processor Series Low Power Integrated x86 Solutions

Integrated Functions (Continued)Bit Name DescriptionTable 4-24. Graphics Pipeline Configuration Registers (Continued)1 PB (RO) Pipeline Busy (Read Only): Indicates that the graphics pipeline is processing data.The “Pipeline Busy” bit differs from the “BLT Busy” bit in that the former only indicates that the graphics pipelineis processing data. The “BLT Busy” bit also indicates that the memory controller has not yet processedall of the requests for the current operation.The “Pipeline Busy” bit must be clear before loading a BLT buffer if the previous BLT operation used thesame BLT buffer.0 BB (RO) BLT Busy (Read Only): Indicates that a BLT / vector operation is in progress.The “BLT Busy” bit must be clear before accessing the frame buffer directly.GX_BASE+8210h-8213h GP_VGA_BASE (R/W) Default Value = xxxxxxxxhNote that the registers at GX_BASE+8210h is located in the area designated for the graphics pipeline but is used for VGA emulationpurposes. Refer to Table 4-39 on page 165 for this register’s bit formats.Geode GXLV Processor SeriesGX_BASE+8214h-8217h GP_VGA_LATCH Register (R/W) Default Value = xxxxxxxxhNote that the registers at GX_BASE+8214h is located in the area designated for the graphics pipeline but is used for VGA emulationpurposes. Refer to Table 4-39 on page 165 for this register’s bit formats.Revision 1.3 133 www.national.com