Geode GXLV Processor Series Low Power Integrated x86 Solutions

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Geode GXLV Processor SeriesInstruction Set (Continued)7.1.1 Prefix (Optional)Prefix bytes can be placed in front of any instruction tomodify the operation of that instruction. When more thanone prefix is used, the order is not important. There arefive types of prefixes that can be used:1. Segment Override explicitly specifies which segmentregister the instruction will use for effective addresscalculation.2. Address Size switches between 16-bit and 32-bitaddressing by selecting the non-default address size.3. Operand Size switches between 16-bit and 32-bitoperand size by selecting the non-default operandsize.4. Repeat is used with a string instruction to cause theinstruction to be repeated for each element of thestring.5. Lock is used to assert the hardware LOCK# signalduring execution of the instruction.Table 7-3 lists the encoding for different types of prefixbytes.Table 7-3. Instruction Prefix SummaryPrefix Encoding DescriptionES: 26h Override segment default, use ESfor memory operand.CS: 2Eh Override segment default, use CSfor memory operand.SS: 36h Override segment default, use SSfor memory operand.DS: 3Eh Override segment default, use DSfor memory operand.FS: 64h Override segment default, use FSfor memory operand.GS: 65h Override segment default, use GSfor memory operand.OperandSizeAddressSize66h67hMake operand size attribute theinverse of the default.Make address size attribute theinverse of the default.LOCK F0h Assert LOCK# hardware signal.REPNE F2h Repeat the following stringinstruction.REP/REPE F3h Repeat the following stringinstruction.7.1.2 OpcodeThe opcode field specifies the operation to be performedby the instruction. The opcode field is either one or twobytes in length and may be further defined by additionalbits in the mod r/m byte. Some operations have more thanone opcode, each specifying a different form of the operation.Certain opcodes name instruction groups. For example,opcode 80h names a group of operations that havean immediate operand and a register or memory operand.The reg field may appear in the second opcode byte or inthe mod r/m byte.The opcode may contain w, d, s and eee opcode fields, forexample, as shown in Table 7-27 on page 217.7.1.2.1 w Field (Operand Size)When used, the 1-bit w field selects the operand size during16-bit and 32-bit data operations. See Table 7-4.wFieldTable 7-4. w Field Encoding16-Bit DataOperationsOperand Size32-Bit DataOperations0 8 bits 8 bits1 16bits 32bits7.1.2.2 d Field (Operand Direction)When used, the 1-bit d field determines which operand istaken as the source operand and which operand is takenas the destination. See Table 7-5.dFieldTable 7-5. d Field EncodingDirection ofOperation0 Register-to-RegisterorRegister-to-Memory1 Register-to-RegisterorMemory-to-RegisterSourceOperandregmod r/mormod ss-indexbaseDestinationOperandmod r/mormod ss-indexbaseregwww.national.com 208 Revision 1.3
Instruction Set (Continued)7.1.2.3 s Field (Immediate Data Field Size)When used, the 1-bit s field determines the size of theimmediate data field. If the s bit is set, the immediate fieldof the opcode is 8 bits wide and is sign-extended to matchthe operand size of the opcode. See Table 7-6.sField0 (or notpresent)Table 7-6. s Field Encoding8-BitOperand SizeImmediate Field Size16-BitOperand Size32-BitOperand Size8 bits 16 bits 32 bits1 8 bits 8 bits(sign-extended)8bits(sign-extended)7.1.2.4 eee Field (MOV-Instruction RegisterSelection)The eee field (bits [5:3]) is used to select the control,debug and test registers in the MOV instructions. The typeof register and base registers selected by the eee field arelisted in Table 7-7. The values shown in Table 7-7 are theonly valid encodings for the eee bits.Table 7-7. eee Field Encodingeee Field Register Type Base Register000 Control Register CR0010 Control Register CR2011 Control Register CR3100 Control Register CR4000 Debug Register DR0001 Debug Register DR1010 Debug Register DR2011 Debug Register DR3110 Debug Register DR6111 Debug Register DR7011 Test Register TR3100 Test Register TR4101 Test Register TR5110 Test Register TR6111 Test Register TR77.1.3 mod and r/m Byte (Memory Addressing)The mod and r/m fields within the mod r/m byte, select thetype of memory addressing to be used. Some instructionsuse a fixed addressing mode (e.g., PUSH or POP) andtherefore, these fields are not present. Table 7-8 lists theaddressing method when 16-bit addressing is used and amod r/m byte is present. Some mod r/m field encodingsare dependent on the w field and are shown in Table 7-9.modFieldTable 7-8. mod r/m Field Encodingr/mField16-Bit AddressMode withmod r/m Byte32-Bit AddressMode with mod r/mByte and No s-i-bByte Present00 000 DS:[BX+SI] DS:[EAX]00 001 DS:[BX+DI] DS:[ECX]00 010 SS:[BP+SI] DS:[EDX]00 011 SS:[BP+DI] DS:[EBX]00 100 DS:[SI] s-i-b is present(See Table 7-15)00 101 DS:[DI] DS:[d32]00 110 DS:[d16] DS:[ESI]00 111 DS:[BX] DS:[EDI]01 000 DS:[BX+SI+d8] DS:[EAX+d8]01 001 DS:[BX+DI+d8] DS:[ECX+d8]01 010 SS:[BP+SI+d8] DS:[EDX+d8]01 011 SS:[BP+DI+d8] DS:[EBX+d8]01 100 DS:[SI+d8] s-i-b is present(See Table 7-15)01 101 DS:[DI+d8] SS:[EBP+d8]01 110 SS:[BP+d8] DS:[ESI+d8]01 111 DS:[BX+d8] DS:[EDI+d8]10 000 DS:[BX+SI+d16] DS:[EAX+d32]10 001 DS:[BX+DI+d16] DS:[ECX+d32]10 010 SS:[BP+SI+d16] DS:[EDX+d32]10 011 SS:[BP+DI+d16] DS:[EBX+d32]10 100 DS:[SI+d16] s-i-b is present(See Table 7-15)10 101 DS:[DI+d16] SS:[EBP+d32]10 110 SS:[BP+d16] DS:[ESI+d32]10 111 DS:[BX+d16] DS:[EDI+d32]Geode GXLV Processor Series11 xxx See Table 7-9. See Table 7-9Note: d8 refers to 8-bit displacement, d16 refers to 16-bit displacement.,and d32 refers to a 32-bit displacement.Revision 1.3 209 www.national.com
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