Geode GXLV Processor Series Low Power Integrated x86 Solutions

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Geode GXLV Processor SeriesProcessor Programming (Continued)3.2 INSTRUCTION SET OVERVIEWThe GXLV processor instruction set can be divided intonine types of operations:• Arithmetic• Bit Manipulation• Shift/Rotate• String Manipulation• Control Transfer• Data Transfer• Floating Point• High-Level Language Support• Operating System SupportThe GXLV processor instructions operate on as few aszero operands and as many as three operands. A NOP(no operation) instruction is an example of a zero-operandinstruction. Two-operand instructions allow the specificationof an explicit source and destination pair as part ofthe instruction. These two-operand instructions can bedivided into ten groups according to operand types:• Register to Register• Register to Memory• Memory to Register• Memory to Memory• Register to I/O• I/O to Register• Memory to I/O• I/O to Memory• Immediate Data to Register• Immediate Data to MemoryTable 3-1. Initialized Core Register Controls (Continued)Register Register Name Initialized Contents CommentsSMHR SMM Header Address 000000h See Table 3-11 on page 54 for bit definitionsSMAR SMM Address 0 000000h See Table 3-11 on page 54 for bit definitions.DIR0 Device Identification 0 4xh Device ID and reads back initial CPU clock-speed setting.See Table 3-11 on page 54 for bit definitions.DIR1 Device Identification 1 xxh Stepping and Revision ID (RO). See Table 3-11 onpage 54 for bit definitions.DR7 Debug Register 7 00000400h See Table 3-13 on page 56 for bit definitions.Note: x = Undefined valueAnoperandcanbeheldintheinstructionitself(asinthecase of an immediate operand), in one of the processor’sregisters or I/O ports, or in memory. An immediate operandis fetched as part of the opcode for the instruction.Operand lengths of 8, 16, 32 or 48 bits are supported aswell as 64 or 80 bits associated with floating-point instructions.Operand lengths of 8 or 32 bits are generally usedwhen executing code written for 386- or 486-class (32-bitcode) processors. Operand lengths of 8 or 16 bits aregenerally used when executing existing 8086 or 80286code (16-bit code). The default length of an operand canbe overridden by placing one or more instruction prefixesin front of the opcode. For example, the use of prefixesallows a 32-bit operand to be used with 16-bit code or a16-bit operand to be used with 32-bit code.Section 7.3 “Processor Core Instruction Set” on page 216contains the clock count table that lists each instruction inthe CPU instruction set. Included in the table are theassociated opcodes, execution clock counts, and effectson the EFLAGS register.3.2.1 Lock PrefixThe LOCK prefix may be placed before certain instructionsthat read, modify, then write back to memory. ThePCI will not be granted access in the middle of lockedinstructions. The LOCK prefix can be used with the followinginstructions only when the result is a write operation tomemory.• Bit Test Instructions (BTS, BTR, BTC)• Exchange Instructions (XADD, XCHG, CMPXCHG)• One-Operand Arithmetic and Logical Instructions(DEC, INC, NEG, NOT)• Two-Operand Arithmetic and Logical Instructions(ADC, ADD, AND, OR, SBB, SUB, XOR).An invalid opcode exception is generated if the LOCK prefixis used with any other instruction or with one of theinstructions above when no write operation to memoryoccurs (for example, when the destination is a register).www.national.com 42 Revision 1.3
Processor Programming (Continued)3.3 REGISTER SETSThe accessible registers in the processor are grouped intothree sets:1) The Application Register Set contains the registersfrequently used by application programmers. Table 3-2 shows the General Purpose, Segment, the InstructionPointer and the EFLAGS Registers.2) The System Register Set contains the registers typicallyreserved for operating systems programmers:Control, System Address, Debug, Configuration, andTest Registers.3) The Model Specific Register (MSR) Set is used tomonitor the performance of the processor or aspecific component within the processor. The ModelSpecific Register set has one 64-bit register calledthe Time Stamp Counter.Each of these register sets are discussed in detail in thesubsections that follow. Additional registers to supportintegrated GXLV processor subsystems are described inSection 4.1 “Integrated Functions Programming Interface”on page 97.3.3.1 Application Register SetThe Application Register Set consists of the registers mostoften used by the applications programmer. These registersare generally accessible, although some bits in theEFLAGS register are protected.The General Purpose Register contents are frequentlymodified by instructions and typically contain arithmeticand logical instruction operands.In real mode, Segment Registers contain the baseaddress for each segment. In protected mode, the segmentregisters contain segment selectors. The segmentselectors provide indexing for tables (located in memory)that contain the base address for each segment, as wellas other memory addressing information.The Instruction Pointer Register points to the nextinstruction that the processor will execute. This register isautomatically incremented by the processor as executionprogresses.The EFLAGS Register contains control bits used toreflect the status of previously executed instructions. Thisregister also contains control bits that affect the operationof some instructions.3.3.1.1 General Purpose RegistersThe General Purpose Registers are divided into four dataregisters, two pointer registers, and two index registers asshown in Table 3-2.The Data Registers are used by the applications programmerto manipulate data structures and to hold theresults of logical and arithmetic operations. Different portionsof general data registers can be addressed by usingdifferent names.An “E” prefix identifies the complete 32-bit register. An “X”suffix without the “E” prefix identifies the lower 16 bits ofthe register.The lower two bytes of a data register are addressed withan “H” suffix (identifies the upper byte) or an “L” suffix (identifiesthe lower byte). These _L and _H portions of thedata registers act as independent registers. For example,if the AH register is written to by an instruction, the AL registerbits remain unchanged.The Pointer and Index Registers are listed below.SI or ESIDI or EDISP or ESPBP or EBPSource IndexDestination IndexStack PointerBase PointerThese registers can be addressed as 16- or 32-bit registers,with the “E” prefix indicating 32 bits. The Pointer and IndexRegisters can be used as general purpose registers; however,some instructions use a fixed assignment of theseregisters. For example, repeated string operations alwaysuse ESI as the source pointer, EDI as the destinationpointer, and ECX as a counter. The instructions that usefixed registers include multiply and divide, I/O access,string operations, stack operations, loop, variable shift androtate, and translate instructions.The GXLV processor implements a stack using the ESPRegister. This stack is accessed during the PUSH andPOP instructions, procedure calls, procedure returns,interrupts, exceptions, and interrupt/exception returns.The GXLV processor automatically adjusts the value ofthe ESP during operations that result from these instructions.The EBP Register may be used to refer to data passed onthe stack during procedure calls. Local data may also beplaced on the stack and accessed with BP. This registerprovides a mechanism to access stack data in high-levellanguages.Geode GXLV Processor SeriesRevision 1.3 43 www.national.com
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Geode GXLV Processor Series Low Pow
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