Geode GXLV Processor Series Low Power Integrated x86 Solutions

Geode GXLV Processor SeriesProcessor Programming (Continued)Bit Name DescriptionTable 3-15. TR7-TR6 Bit DefinitionsTR7 RegisterTLB Test Data Register (R/W)31:12 PhysicalAddressPhysical Address:TLB lookup: Data field from the TLB.TLB write: Data field written into the TLB.11:10 RSVD Reserved: Set to 0.9:7 TLB LRU LRU Bits:TLB lookup: LRU bits associated with the TLB entry before the TLB lookup.TLB write: Ignored.6:5 RSVD Reserved: Set to 0.4 PL PL Bit:TLB lookup: If PL = 1, read hit occurred. If PL = 0, read miss occurred.TLB write: If PL = 1, REP field is used to select the set. If PL = 0, the pseudo-LRU replacement algorithmis used to select the set.3:2 REP Set Selection:TLB lookup: If PL = 1, this field indicates the set in which the tag was found. If PL = 0, undefined data.TLB write: If PL = 1, this field selects one of the four sets for replacement. If PL = 0, ignored.1:0 RSVD Reserved: Set to 0.TR6 RegisterTLB Test Control Register (R/W)31:12 LinearAddressLinear Address:TLB lookup: The TLB is interrogated per this address. If one and only one match occurs in the TLB, therest of the fields in TR6 and TR7 are updated per the matching TLB entry.TLB write: A TLB entry is allocated to this linear address.11 V Valid Bit:TLB write: If V = 1, the TLB entry contains valid data. If V = 0, target entry is invalidated.10:98:76:5D, D#U, U#R, R#4:1 RSVD Reserved: Set to 0.0 C Command Bit:If C = 1: TLB lookup.If C = 0: TLB write.Dirty Attribute Bit and its Complement (D, D#):User/Supervisor Attribute Bit and its Complement (U, U#):Read/Write Attribute Bit and its Complement (R, R#):Effect on TLB LookupEffect on TLB Write00 = Do not match Undefined01 = Match if D, U, or R bit is a 0 Clear the bit10 = Match if D, U, or R bit is a 1 Set the bit11 = Match if D, U, or R bit is either a 1 or 0 Undefinedwww.national.com 58 Revision 1.3